WS512K32V-XXX
HI-RELIABILITY PRODUCT
512Kx32 SRAM 3.3V MODULE PRELIMINARY*
FEATURES
■ Access Times of 15, 17, 20ns
■ Low Voltage Operation
■ Packaging
■ Low Power CMOS
■ TTL Compatible Inputs and Outputs
■ Fully Static Operation:
• 66-pin, PGA Type, 1.075 inch square, Hermetic
Ceramic HIP (Package 400)
• No clock or refresh required.
■ Three State Output.
• 68 lead, 22.4mm (0.88") CQFP, 4.6mm (0.180") high,
(Package 509)
■ Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
■ Weight
• 68 lead, 23.9mm (0.940" sq.) Low Profile CQFP (G1U),
3.56mm (0.140") high, (Package 519)
■ Organized as 512Kx32; User Configurable as 1Mx16 or 2Mx8
■ Commercial, Industrial and Military Temperature Ranges
■ Low Voltage Operation:
WS512K32V-XG2TX - 8 grams typical
WS512K32V-XG1UX - 5 grams typical
WS512K32NV-XH1X - 13 grams typical
*
This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
• 3.3V ± 10% Power Supply
PIN CONFIGURATION FOR WS512K32NV-XH1X
TOP VIEW
PIN DESCRIPTION
1
12
23
34
45
56
I/O0-31 Data Inputs/Outputs
A0-18
WE1-4
CS1-4
OE
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
I/O
I/O
8
9
WE
2
I/O15
I/O14
I/O13
I/O12
OE
I/O24
I/O25
I/O26
V
CC
I/O31
I/O30
I/O29
I/O28
CS2
CS
4
I/O10
GND
I/O11
WE
4
VCC
A
A
A
A
A
13
14
15
16
17
A
A
6
7
I/O27
GND
NC
A10
A11
A12
VCC
A
A
3
4
5
3
3
A
A
A
0
1
2
Not Connected
A18
NC
BLOCK DIAGRAM
WE1
A
8
9
A
WE1CS1
WE2CS2
WE3CS3
WE4CS4
I/O
I/O
I/O
I/O
7
A
WE
CS
I/O23
I/O22
I/O21
I/O20
OE
0-18
A
I/O
I/O
I/O
0
1
2
CS
NC
I/O
1
6
I/O16
I/O17
I/O18
512K x 8
512K x 8
512K x 8
512K x 8
5
4
GND
I/O19
3
8
8
8
8
11
22
33
44
55
66
I/O16-23
I/O24-31
I/O0-7
I/O8-15
May 2001 Rev. 6
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com