WS512K32V-XXX
White Electronic Designs
PRELIMINARY*
512Kx32 SRAM 3ꢀ3V MULTICHIP PACKAGE
FEATURES
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Low Voltage Operation:
3ꢀ3V ± 10% Power Supply
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Access Times of 15, 17, 20ns
Low Voltage Operation
Packaging
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Low Power CMOS
TTL Compatible Inputs and Outputs
Fully Static Operation:
66-pin, PGA Type, 1ꢀ075 inch square, Hermetic
Ceramic HIP (Package 400)
No clock or refresh requiredꢀ
Three State Outputꢀ
68 lead, 23ꢀ9mm (0ꢀ940 inch) sqꢀ, Low Profile CQFP,
(G1T), 4ꢀ06 (0ꢀ160 inch) high, (Package 524)
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Built-in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation
68 lead, 22ꢀ4mm (0ꢀ880 inch) CQFP, (G2U),
3ꢀ56mm (0ꢀ140"), (Package 510)
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Weight
68 lead, 23ꢀ9mm (0ꢀ940 inch) sqꢀ, Low Profile
CQFP, (G1U)1, 3ꢀ56mm (0ꢀ140 inch) high,
(Package 519)
WS512K32V-XG1TX - 5 grams typical
WS512K32V-XG1UX1 - 5 grams typical
WS512K32V-XG2UX - 8 grams typical
WS512K32NV-XH1X - 13 grams typical
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Organized as 512Kx32; User Configurable as
1Mx16 or 2Mx8
Note 1: Package Not Recommended For New Design
*This data sheet describes a product under development, not fully
characterized, and is subject to change without notice$
Commercial, Industrial and Military Temperature
Ranges
PIN CONFIGURATION FOR WS512K32NV-XH1X
TOP VIEW
PIN DESCRIPTION
I/O0-31 Data Inputs/Outputs
A0-18
WE1-4
CS1-4
OE
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
1
12
23
34
45
56
I/O8
I/O9
I/O10
A13
WE2
CS2
GND
I/O11
A10
I/O15
I/O14
I/O13
I/O12
OE
I/O24
I/O25
I/O26
A6
VCC
CS4
WE4
I/O27
A3
I/O31
I/O30
I/O29
I/O28
A0
VCC
GND
NC
Not Connected
A14
A7
A15
A11
A18
NC
A4
A1
BLOCK DIAGRAM
A16
A12
WE1
I/O7
I/O6
I/O5
I/O4
A8
A5
A2
WE3 CS3
WE4 CS4
WE1 CS1
WE2 CS2
A17
VCC
CS1
NC
A9
WE3
CS3
GND
I/O19
I/O23
I/O22
I/O21
I/O20
OE
I/O0
I/O1
I/O2
I/O16
I/O17
I/O18
A0-18
512K x 8
512K x 8
512K x 8
512K x 8
I/O3
11
22
33
44
55
66
8
8
8
8
I/O16-23
I/O24-31
I/O0-7
I/O8-15
March2003Revꢀ8
1
White Electronic Designs Corporation (602) 437-1520 wwwꢀwhiteedcꢀcom