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WF4M16-90DTC5 PDF预览

WF4M16-90DTC5

更新时间: 2024-10-02 03:17:03
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WEDC 闪存
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11页 126K
描述
2x2Mx16 5V FLASH MODULE

WF4M16-90DTC5 数据手册

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WF4M16-XDTX5  
HI-RELIABILITY PRODUCT  
2x2Mx16 5V FLASH MODULE ADVANCED*  
FEATURES  
Data Polling and Toggle Bit feature for detection of program  
Access Time of 90, 120, 150ns  
Packaging:  
or erase cycle completion.  
Supports reading or programming data to a sector not being  
• 56 Lead, Hermetic Ceramic, 0.520" CSOP (Package 213).  
Fits standard 56 SSOP footprint.  
erased.  
Built-in Decoupling Caps and Multiple Ground Pins for Low  
Noise Operation, Separate Power and Ground Planes to  
improve noise immunity  
Sector Architecture  
• 32 equal size sectors of 64KBytes per each 2Mx8 chip  
Any combination of sectors can be erased. Also supports  
full chip erase.  
RESET pin resets internal state machine to the read mode.  
Ready/Busy (RY/BY) output for direction of program or erase  
Minimum 100,000 Write/Erase Cycles Minimum  
cycle completion.  
Organized as two banks of 2Mx16; User Configurable as  
4 x 2Mx8  
*
This data sheet describes a product that may or may not be under  
development and is subject to change or cancellation without notice.  
Commercial, Industrial, and Military Temperature Ranges  
5 Volt Read and Write. 5V ± 10% Supply.  
Low Power CMOS  
Note: For programming information refer to Flash Programming 16M5  
Application Note.  
FIG. 1 PIN CONFIGURATION FOR WF4M16-XDTX5  
56 CSOP  
PIN DESCRIPTION  
TOP VIEW  
I/O0-15 Data Inputs/Outputs  
CS1  
A12  
A13  
A14  
A15  
NC  
1
2
3
4
5
6
7
8
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
NC  
RESET  
A11  
A10  
A9  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
GND  
A8  
BLOCK DIAGRAM  
A0-20  
WE  
Address Inputs  
Write Enable  
Chip Selects  
Output Enable  
Power Supply  
Ground  
I/O0-7  
I/O8-15  
RESET  
WE  
OE  
A0-20  
CS1-4  
OE  
CS2  
NC  
A20  
A19  
A18  
A17  
A16  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
RY/BY  
VCC  
GND  
RY/BY  
RESET  
2M x 8  
2M x 8  
2M x 8  
2M x 8  
V
CC  
Ready/Busy  
Reset  
GND  
I/O6  
I/O14  
I/O7  
I/O15  
RY/BY  
OE  
WE  
NC  
I/O13  
I/O5  
I/O12  
I/O4  
V
CC  
I/O9  
I/O1  
CS  
CS  
CS  
CS  
1
2
3
4
39 I/O8  
38 I/O0  
37 A0  
36 NC  
35 CS3  
34 CS4  
33 I/O2  
NOTE:  
1. RY/BY is an open drain output and should be pulled-up to Vcc with an  
external resistor.  
I/O10  
I/O3  
I/O11  
GND  
32  
31  
30  
29  
2. CS1 and CS3 control the same data bus. Reads cannot be done with CS1  
and CS3 both active. CS2 and CS4 control the same data bus. Reads  
cannot be done with CS2 and CS4 both active.  
VCC  
3. Address compatible with Intel 2M8 56 SSOP.  
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com  
November 1999 Rev.3  

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