Datasheet > WEDPN16M64VR-125BC

WEDPN16M64VR-125BC

更新时间： 2023-02-26 15:27:22

品牌	Logo	应用领域
美高森美 - MICROSEMI		动态存储器
页数	文件大小	规格书
13页	423K
描述
Synchronous DRAM Module, 16MX64, 5.8ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219

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WEDPN16M64VR-XBX

16MX64REGISTEREDSYNCHRONOUSDRAM

FEATURES

GENERAL DESCRIPTION

! Registered for enhanced performace of bus speeds

The 128MByte (1Gb) SDRAMis a high-speed CMOS, dynamic

random-access,memoryusing4 chipscontaining268,435,456

bits. Each chip is internally configured as a quad-bank DRAM

with a synchronous interface. Each of the chip’s 67,108,864-

bit banks is organized as 8,192 rows by 512 columns by 16

bits. The MCP also incorporates two 16-bit universal bus

drivers for input control signals and addresses.

• 66, 100, 125, 133** MHz

! Package:

• 219 Plastic Ball Grid Array (PBGA), 32 x 25mm

! Single 3.3V ± 0.3V power supply

! Fully Synchronous; all signals registered on positive edge

Read and write accesses to the SDRAM are burst oriented;

accesses start at a selected location and continue for a

programmed number of locations in a programmed se-

quence. Accesses begin with the registration of an ACTIVE

command, which is then followed by a READ or WRITE

command. The address bits registered coincident with the

ACTIVE command are used to select the bank and row to be

accessed (BA0, BA1 select the bank; A0-12 select the row).

The address bits registered coincident with the READ or

WRITE command are used to select the starting column

location for the burst access.

of system clock cycle

! Internal pipelined operation; column address can be

changed every clock cycle

! Internal banks for hiding row access/precharge

! Programmable Burst length 1,2,4,8 or full page

! 8,192 refresh cycles

! Commercial, Industrial and Military Temperature Ranges

! Organized as 16M x 64

• User configureable as 32M x 32

The SDRAM provides for programmable READ or WRITE burst

lengths of 1, 2, 4 or 8 locations, or the full page, with a burst

terminate option. An AUTO PRECHARGE function may be

enabled to provide a self-timed row precharge thatisinitiated

at the end of the burst sequence.

! Weight: WEDPN16M64VR-XBX - 2.5 grams typ ical

BENEFITS

! 37% SPACE SAVINGS

The 1Gb SDRAM uses an internal pipelined architecture to

achieve high-speed operation. This architecture is compat-

ible with the 2n rule of prefetch architectures, but it also

allows the column address to be changed on every clock

cycle to achieve ahigh-speed,fullyrandomaccess.Precharging

one bank while accessing one of the other three banks will

hide the precharge cycles and provide seamless, high-

speed, random-access operation.

! 17% I/O Reduction

! Reduced part count

! Reduced trace lengths for lower parasitic capacitance

! Glue-less connection to memory controller/PCI Bridge

! Suitable for hi-reliability applications

! Laminate interposer for optimum TCE match

! Upgradeable to 32M x 64 density (contact factory for

The 1Gb SDRAM is designed to operate in 3.3V, low-power

memory systems. An auto refresh mode is provided, along

with a power-saving, power-down mode.

information)

*This data sheet describes a product that is subject to change without notice.

**Available in commercial and industrial temperatures only.

All inputs and outputs are LVTTL compatible. SDRAMs offer

substantial advances in DRAM operating performance, in-

cluding the ability to synchronously burst data at a high data

rate with automatic column-address generation, the ability to

interleave between internal banks in order to hide precharge

time and the capability to randomly change column ad-

dresses on each clock cycle during a burst access.

November 2003 Rev. 4

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

12 3 4 5 6 7...13

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与WEDPN16M64VR-125BC相关器件

型号	品牌	获取价格	描述	数据表
WEDPN16M64VR-125BI	MICROSEMI	获取价格	Synchronous DRAM Module, 16MX64, 5.8ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219
WEDPN16M64VR-125BM	WEDC	获取价格	Synchronous DRAM Module, 16MX64, 5.8ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219
WEDPN16M64VR-133B2C	WEDC	获取价格	16Mx64 REGISTERED SYNCHRONOUS DRAM
WEDPN16M64VR-133B2I	MICROSEMI	获取价格	Synchronous DRAM Module, 16MX64, 5.4ns, CMOS, PBGA219, 25 X 21 MM, PLASTIC, BGA-219
WEDPN16M64VR-133B2I	WEDC	获取价格	16Mx64 REGISTERED SYNCHRONOUS DRAM
WEDPN16M64VR-133B2M	WEDC	获取价格	16Mx64 REGISTERED SYNCHRONOUS DRAM
WEDPN16M64VR-133B2M	MICROSEMI	获取价格	Synchronous DRAM Module, 16MX64, 5.4ns, CMOS, PBGA219, 25 X 21 MM, PLASTIC, BGA-219
WEDPN16M64VR-133BC	MICROSEMI	获取价格	Synchronous DRAM Module, 16MX64, 5.4ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219
WEDPN16M64VR-133BI	MICROSEMI	获取价格	Synchronous DRAM Module, 16MX64, 5.4ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219
WEDPN16M64VR-66BC	WEDC	获取价格	Synchronous DRAM Module, 16MX64, 7.5ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219

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