Datasheet > WED3DG644V100D1-SG

WED3DG644V100D1-SG

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
WEDC		动态存储器
页数	文件大小	规格书
8页	186K
描述
32MB - 4Mx64 SDRAM, UNBUFFERED

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WED3DG644V-D1

White Electronic Designs

AC OPERATING TEST CONDITIONS

V_CC= 3.3V ± 0.3V, 0 ≤ T_A≤ 70°C

Parameter

Value

Unit

AC input levels (V_IH/V_IL)

2.4/0.4

1.4

Input timing measurement reference level

Input rise and fall time

t_R/t_F= 1/1

1.4

Output timing measurement reference level

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Version

Parameter

Symbol

Unit

Note

7.5, 10

Row active to row active delay

RAS# to CAS# delay

t_RRD(min)

t_RCD(min)

Row precharge time

_RP(min)

t_RAS(min)

Row active time

_RAS(max)

t_RC(min)

t_RDL(min)

100

Row cycle time

Last data in to row precharge

Last data in to Active delay

Last data in to new col. address delay

Last data in to burst stop

CLK

—

_DAL(min)

2 CLK + t_RP

t_CDL(min)

t_BDL(min)

t_CCD(min)

CLK

Col. address to col. address delay

CAS latency=3

CAS latency=2

Number of valid output data

Notes :

The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer.

Minimum delay is required to complete write.

All parts allow every cycle column address change.

In case of row precharge interrupt, auto precharge and read burst stop.

June 2006

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

1 2 3 456 7 8

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