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WC32P020-16P2M PDF预览

WC32P020-16P2M

更新时间: 2024-01-22 04:05:19
品牌 Logo 应用领域
WEDC 时钟外围集成电路
页数 文件大小 规格书
14页 476K
描述
Microprocessor, 32-Bit, 16.67MHz, CMOS, CPGA114, CERAMIC, PGA-114

WC32P020-16P2M 技术参数

生命周期:TransferredReach Compliance Code:unknown
风险等级:5.75Is Samacsys:N
地址总线宽度:32位大小:32
边界扫描:NO最大时钟频率:16.67 MHz
外部数据总线宽度:32格式:FIXED POINT
集成缓存:NOJESD-30 代码:S-CPGA-P114
低功率模式:NODMA 通道数量:
外部中断装置数量:7串行 I/O 数:
端子数量:114片上数据RAM宽度:
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装形状:SQUARE
封装形式:GRID ARRAY认证状态:Not Qualified
RAM(字数):0速度:16.67 MHz
最大压摆率:333 mA最大供电电压:5.25 V
最小供电电压:4.75 V标称供电电压:5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子形式:PIN/PEG
端子位置:PERPENDICULARuPs/uCs/外围集成电路类型:MICROPROCESSOR
Base Number Matches:1

WC32P020-16P2M 数据手册

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WC32P020-XXM  
White Electronic Designs  
68020 FEATURES  
Selection of Processor Speeds: 16.67, 20, 25 MHz  
Military Temperature Range: -55°C to +125°C  
Packaging  
High-Performance Asynchronous Bus Is  
Nonmultiplexed and Full 32-Bits  
Dynamic Bus Sizing Efficiently Supports 8-/16-/32-  
Bit Memories and Peripherals  
Full Support of Virtual Memory and Virtual Machine  
16 32-Bit General-Purpose Data and Address  
Registers  
Two 32-Bit Supervisor Stack Pointers and Five  
Special-Purpose Control Registers  
114 pin Ceramic PGA (P2)  
132 lead Ceramic Quad Flatpack, CQFP (Q2)  
Object-code compatible with earlier 68000  
Microprocessors  
Addressing mode extensions for enhanced support  
of high-level languages  
Bit Field Data Type Accelerates Bit-Oriented  
Applications–i.e., Video Graphics  
Fast On-Chip Instruction Cache Speeds  
Instructions and Improves Bus Bandwidth  
Coprocessor Interface to Companion 32-Bit  
Peripherals–the 68881 and 68882 Floating-Point  
Coprocessors and the 68851 Paged Memory  
Management Unit  
18 Addressing Modes and 7 Data Types  
4 GigaByte Direct Addressing Range  
DESCRIPTION  
The WC32P020 is a 32-bit implementation of the 68000  
Family of microprocessors. Using HCMOS technology,  
the WC32P020 is implemented with 32-bit registers and  
data paths, 32-bit addresses, a powerful instruction set,  
and flexible addressing modes.  
Pipelined Architecture with High Degree of Internal  
Parallelism allowing Multiple Instructions to be  
executed concurrently  
FIGURE 1 – BLOCK DIAGRAM  
MICRO MACHINE  
SEQUENCER  
MICROROM  
NANOROM  
INSTRUCTION DECODE  
INSTRUCTION PIPE  
CONTROL SECTION  
EXECUTION UNIT  
INSTRUCTION OPERAND  
TAG  
CACHE  
INSTRUCTION  
CACHE  
DATA  
SECTION  
ADDRESS  
SECTION  
ADDRESS  
SECTION  
BUS  
CONTROLLER  
ADDRESS  
PADS  
DATA  
PADS  
BUS CONTROLLER  
White Electronic Designs Corp. reserves the right to change products or specifications without notice.  
December 2002  
Rev. 2  
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  

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