WC32P040-XXM
White Electronic Designs
68040 FEATURES
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Selection of Processor Speeds: 25, 33MHz
Military Temperature Range: -55°C to +125°C
Packaging
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32-Bit, Nonmultiplexed External Address and Data
Buses with Synchronous Interface
User Object-Code Compatible with all Earlier 68000
Microprocessors
• 179 pin Ceramic PGA (P4)
4-GigaByte Direct Addressing Range
• 184 lead Ceramic Quad Flatpack, CQFP (Q4)
6-Stage Pipeline, 68030-Compatible IU
68881/68882-Compatible FPU
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DESCRIPTION
The WC32P040 is a 68000-compatible, high-performance,
32-bit microprocessor. The WC32P040 is a virtual
memory microprocessor employing multiple concurrent
execution units and a highly intergrated architecture that
provides very high performance in a monolithic HCMOS
device. It has a 68030-compatible integer unit (IU) and
two independent caches. The WC32P040 contains dual,
independent, demand-paged memory management units
(MMUs) for instruction and data stream accesses and
independent, 4-Kbyte instruction and data caches. The
WC32P040 has a 68881/68882-compatible floating-point
unit (FPU).
Independent Instruction and Data MMUs
Simultaneously Accessible, 4-Kbyte Physical
Instruction Cache and 4-Kbyte Physical Data Cache
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Low-Latency Bus Acceses for Reduced Cache Miss
Penalty
Multimaster/Multiprocessor Support via Bus
Snooping
Concurrent IU, FPU, MMU, and Bus Controller
Operation Maximizes Throughput
FIGURE 1 – BLOCK DIAGRAM
INSTRUCTION DATA BUS
INSTRUCTION
ATC
INSTRUCTION
CACHE
INSTRUCTION
ADDRESS
INSTRUCTION
MMU/CACHE/SNOOP
CONTROLLER
INSTRUCTION
FETCH
B
U
S
CONVERT
EXECUTE
DECODE
INSTRUCTION MEMORY UNIT
DATA MEMORY UNIT
ADDRESS
BUS
C
O
N
T
EA
CALCULATE
EA
R
O
L
FETCH
DATA
BUS
EXECUTE
L
DATA
WRITE-
BACK
E
R
DATA
ADDRESS
WRITE-
BACK
MMU/CACHE/SNOOP
CONTROLLER
BUS
CONTROL
SIGNALS
INTEGER
UNIT
FLOATING-
POINT
DATA
ATC
DATA
UNIT
CACHE
OPERAND DATA BUS
July 1998
July 1998
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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com