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W83L785TG-L PDF预览

W83L785TG-L

更新时间: 2024-02-03 12:57:11
品牌 Logo 应用领域
华邦 - WINBOND /
页数 文件大小 规格书
18页 318K
描述
Sensor/Transducer,

W83L785TG-L 技术参数

生命周期:ObsoleteReach Compliance Code:unknown
风险等级:5.84传感器/换能器类型:TEMPERATURE SENSOR,SWITCH/DIGITAL OUTPUT,SERIAL
Base Number Matches:1

W83L785TG-L 数据手册

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W83L785TS-L/TG-L  
6. FUNCTIONAL DESCRIPTION  
6.1 General Description  
Winbond W83L785TS-L/TG-L, a low-cost, fully integrated temperature sensor, issues an alert signal  
when the monitored temperature exceeds the threshold. W83L785TS-L/TG-L provides 1 remote  
temperature sensor which could be connected to CPU thermal diode. There is 1 dedicated OFFSET/  
FAULT_LIMIT pin to compensate inaccuracy of CPU temperature by adjusting external two serial  
resistors and set up temperature fault threshold. When W83L785TS-L/TG-L starts the monitoring  
functions, the Watch Dog machine monitors every function and stores the value to registers. If the  
monitored value exceeds the limit value, the interrupt status will be set to 1. W83L785TS-L/TG-L  
communicates over a two-wire serial interface compatible with SMBus standards.  
6.2 Access Interface  
W83L785TS-L/TG-L provides I2C Serial Bus to read/write internal registers. In the W83L785TS-L/TG-L,  
the I2C address defined value is 0101110.  
6.2.1 The first serial bus access timing is shown as follows:  
(a) Serial bus write to internal address register followed by the data byte  
0
7
8
0
7
8
SCL  
SDA  
0
1
0
1
1
1
0
R/W  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
8
D0  
Start By  
Master  
Ack  
by  
Ack  
by  
Frame 1  
Frame 2  
785TR  
785TR  
Serial Bus Address Byte  
Internal Index Register Byte  
0
7
SCL(Continued)  
SDA (Continued)  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Ack  
by  
Stop  
by  
785TR  
Master  
Frame 3  
Data Byte  
Figure 1. Serial Bus Write to Internal Address Register followed by the Data Byte  
(b) Serial bus read form internal address register followed by the data byte  
0
7
8
0
7
8
SCL  
SDA  
0
0
1
0
1
1
R/W  
D7  
D6  
8
D5  
D4  
D3  
D2  
D1  
D0  
1
ack  
by  
ack  
by  
Frame 1  
Frame 2  
785TR  
Serial Bus Address Byte  
785TR  
Internal Index Register Byte  
0
1
1
2
3
4
5
1
6
7
0
1
2
3
4
5
6
7
8
SCL(Continued)  
SDA(Continued)  
0
0
1
1
0
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
R/W  
Repeat start  
by Master  
Ack  
Stop by  
Master  
Nack  
ack  
by  
Data Byte from 785TR  
by  
by  
784R  
Frame 3  
Serial Bus Byte  
Frame 4  
Master  
785TR  
Figure 2. Serial Bus read from Internal Address Register followed by the Data Byte  
Publication Release Date: April, 2006  
Revision 1.1  
- 3 -  

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