PRELIMINARY
W204
Spread Spectrum FTG for 440BX and VIA Apollo Pro-133
CPU Cycle to Cycle Jitter: ..........................................250 ps
CPU0:3 Output Skew: ................................................175 ps
Features
• Maximized EMI suppression using Cypress’s spread
spectrum technology
• Optimizedsystemfrequencysynthesizerfor440BXand
VIA Apollo Pro-133
• Four copies of CPU output
• Eight copies of PCI clock (synchronous w/CPU output)
• Two copies of 14.318-MHz IOAPIC output and three
buffered copies of 14.318-MHz reference input
• One copy of 48-MHz USB output
• Selectable 24-/48-MHz clock-through-resistor
strapping
PCI_F, PCI1:7 Output Skew:.......................................500 ps
CPU to PCI Output Skew: ............... 1.0–4.0 ns (CPU Leads)
REF0/SEL48#, SCLK,SDATA:........................... 250K pull-up
FS1:...............................................................250K pull-down
FS0:...................................................No pull-up or pull-down
Test mode and output three-state through SMBus interface
Table 1. Pin Selectable Frequency
FS1
1
FS0
1
CPU(0:3)
133.3 MHz
105 MHz
100 MHz
66.8 MHz
PCI
• Power management control input pins
• Programmable clock outputs up to 155 MHz via SMBus
interface (32 selectable frequencies)
33.3 MHz
35 MHz
1
0
0
1
33.3 MHz
33.3 MHz
Key Specifications
0
0
Supply Voltages:.....................................VDDQ3 = 3.3V±5%
VDDQ2 = 2.5V±5%
[1]
Block Diagram
Pin Configuration
VDDQ3
REF0/SEL48#
REF1
GND
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDQ3
REF0/SEL48#
REF1
2
REF2
VDDQ2
APIC0
APIC1
GND
3
X1
X2
XTAL
OSC
X1
4
REF2
GND
X2
5
PLL Ref Freq
GND
6
PCI_F
PCI1
7
NC
VDDQ2
8
VDDQ2
CPU0
CPU1
GND
VDDCORE0/1
GNDCORE0/1
APIC0
VDDQ3
PCI2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
APIC1
GND
PCI3
GND
VDDQ2
CPU2
CPU3
GND
VDDQ2
PCI4
CPU_STOP#
PCI5
CPU0
VDDQ3
PCI6
CPU1
GND
VDDQ2
Stop
Clock
Control
VDDQ3
GND
PCI7
GND
PCI_STOP#
CPU_STOP#
PWR_DWN#
SPREAD#
SDATA
CPU2
VDDQ3
GND
FS0:1
PLL 1
CPU3
VDDQ3
48MHz
24_48MHz/FS1
GND
÷2/÷3
GND
VDDQ3
SCLK
SPREAD#
FS0
PCI_F
PCI1
PCI2
Note:
Stop
Clock
Control
1. Internal pull-up resistors should not be relied upon for setting I/O
pins HIGH.
PCI3
GND
PCI_STOP#
VDDQ3
PCI4
2
PCI5
PCI6
SDATA
SCLK
I C
Logic
PCI7
GND
Power
PWR_DWN#
Down
Control
VDDQ3
48MHz
PLL2
24_48MHz/FS1
GND
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07264 Rev. *A
Revised December 22, 2002