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W19B320ATB PDF预览

W19B320ATB

更新时间: 2024-02-04 07:14:13
品牌 Logo 应用领域
华邦 - WINBOND /
页数 文件大小 规格书
53页 480K
描述
4M × 8/2M × 16 BITS 3V FLEXIBLE BANK FLASH MEMORY

W19B320ATB 技术参数

生命周期:Obsolete零件包装代码:TSOP
包装说明:TSOP-48针数:48
Reach Compliance Code:unknownECCN代码:3A991.B.1.A
HTS代码:8542.32.00.51风险等级:5.56
最长访问时间:70 ns其他特性:TOP BOOT BLOCK
备用内存宽度:8启动块:TOP
JESD-30 代码:R-PDSO-G48长度:18.4 mm
内存密度:33554432 bit内存集成电路类型:FLASH
内存宽度:16功能数量:1
端子数量:48字数:2097152 words
字数代码:2000000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-20 °C
组织:2MX16封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
编程电压:3 V认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
类型:NOR TYPE宽度:12 mm
Base Number Matches:1

W19B320ATB 数据手册

 浏览型号W19B320ATB的Datasheet PDF文件第4页浏览型号W19B320ATB的Datasheet PDF文件第5页浏览型号W19B320ATB的Datasheet PDF文件第6页浏览型号W19B320ATB的Datasheet PDF文件第8页浏览型号W19B320ATB的Datasheet PDF文件第9页浏览型号W19B320ATB的Datasheet PDF文件第10页 
W19B320AT/B  
6. FUNCTIONAL DESCRIPTION  
6.1 Device Bus Operation  
6.1.1 Word/Byte Configuration  
The #BYTE pin controls the device data I/O pins operate whether in the byte or word configuration.  
When the #BYTE pin is ‘1’, the device is in word configuration; DQ0 -DQ15 are active and controlled  
by #CE and #OE.  
When the #BYTE pin is ‘0’, the device is in byte configuration, and only data I/O pins DQ0-DQ7 are active  
and controlled by #CE and #OE. The data I/O pins DQ8-DQ14 are tri-stated, and the DQ15 pin is  
used as an input for the LSB (A-1) address function.  
6.1.2 Reading Array Data  
To read array data from the outputs, the #CE and #OE pins must be set to VIL. #CE is the power  
control and used to select the device. #OE is the output control and gates array data to the output  
pins. #WE should stay at VIH. The #BYTE pin determines the device outputs array data whether in  
words or bytes.  
The internal state machine is set for reading array data when device power-up, or after hardware  
reset. This ensures that no excess modification of the memory content occurs during the power  
transition. In this mode there is no command necessary to obtain array data. Standard microprocessor  
read cycles that assert valid addresses on the device address inputs produce valid data on the device  
data outputs. Each bank remains enabled for read access until the command register contents are  
changed.  
6.1.3 Writing Commands/Command Sequences  
In writhing a command or command sequence (which includes programming data to the device and  
erasing sectors of memory), the system must drive #WE and #CE to VIL, and #OE to VIH.  
For program operations, the #BYTE pin determines the device accepts program data whether in bytes  
or in words. Refer to “Word/Byte Configuration” for more information.  
The Unlock Bypass mode of device is to facilitate a faster programming. When a bank enters the  
Unlock Bypass mode, only two write cycles are required to program a word or byte. Please refer to  
"Word/Byte Configuration” section for details on programming data to the device using both standard  
and Unlock Bypass command sequences.  
The erase operation can erase a sector, multiple sectors, even the entire device. The device address  
space is divided into four banks: Bank 1and Bank 4 contains the boot/parameter sectors; while Bank 2  
and Bank 3 contain the larger sectors of uniform size. The “bank address” is the address bits required  
to solely select a bank; while the “sector address” is the address bits required to solely select a sector.  
Publication Release Date: December 27, 2005  
- 7 -  
Revision A4  
 

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