Datasheet > W134M_05

W134M_05

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟发生器
页数	文件大小	规格书
12页	208K
描述
Direct Rambus⑩ Clock Generator

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

W134M_05 数据手册

W134M/W134S

Pin Definitions

Pin Name

No.

Type

Description

REFCLK

Reference Clock Input. Reference clock input, normally supplied by a system frequency

synthesizer (Cypress W133).

PCLKM

Phase Detector Input. The phase difference between this signal and SYNCLKN is used

to synchronize the Rambus Channel Clock with the system clock. Both PCLKM and

SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If Gear Ratio

Logic is not used, this pin would be connected to Ground.

Phase Detector Input. The phase difference between this signal and PCLKM is used to

synchronize the Rambus Channel Clock with the system clock. Both PCLKM and

SYNCLKN are provided by the Gear Ratio Logic in the memory controller. If Gear Ratio

Logic is not used, this pin would be connected to Ground.

SYNCLKN

STOPB

Clock Output Enable. When this input is driven to active LOW, it disables the differential

Rambus Channel clocks.

PWRDNB

MULT 0:1

Active LOW Power-down. When this input is driven to active LOW, it disables the differ-

ential Rambus Channel clocks and places the W134M/W134S in power-down mode.

15, 14

PLL Multiplier Select. These inputs select the PLL prescaler and feedback dividers to

determine the multiply ratio for the PLL for the input REFCLK.

W134S

W134M

PLL/REFCLK

MULT0

MULT1

4.5

5.333

CLK, CLKB

S0, S1

20, 18

24, 23

Complementary Output Clock. Differential Rambus Channel clock outputs.

Mode Control Input. These inputs control the operating mode of the W134M/W134S.

MODE

Normal

Output Enable Test

Bypass

Test

VDDIR

VDDIPD

–

No Connect

RefV Reference for REFCLK. Voltage reference for input reference clock.

RefV Reference for Phase Detector. Voltage reference for phase detector inputs and StopB.

VDD

3, 9, 16, 22

Power Connection. Power supply for core logic and output buffers. Connected to 3.3V

supply.

GND

4, 5, 8, 13, 17,

Ground Connection. Connect all ground pins to the common system ground plane.

W134M/W134S

W133

W158

W159

W161

W167

Refclk

Phase

PLL

Busclk

Align

CY2210

RAC

RMC

Pclk

DLL

Synclk

Gear

Ratio

Logic

Figure 1. DDLL System Architecture

Document #: 38-07426 Rev. *C

Page 2 of 12

123 4 5 6 7...12

下载PDF

与W134M_05相关器件

型号	品牌	描述	获取价格	数据表
W134MH	CYPRESS	Direct Rambus⑩ Clock Generator	获取价格
W134MHT	CYPRESS	Direct Rambus⑩ Clock Generator	获取价格
W134MSQC	CYPRESS	Processor Specific Clock Generator, CMOS, PDSO24, 0.150 INCH, LEAD FREE, SSOP-24	获取价格
W134MSQCT	CYPRESS	Processor Specific Clock Generator, CMOS, PDSO24, 0.150 INCH, LEAD FREE, SSOP-24	获取价格
W134S	CYPRESS	Direct Rambus Clock Generator	获取价格
W134SH	CYPRESS	Direct Rambus Clock Generator	获取价格