Datasheet > W134

W134

更新时间： 2024-02-16 00:24:32

品牌	Logo	应用领域
其他 - ETC		时钟
页数	文件大小	规格书
12页	188K
描述
Clocks and Buffers

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

W134 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	SSOP	包装说明：	0.150 INCH, LEAD FREE, SSOP-24
针数：	24	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.76	Is Samacsys：	N
JESD-30 代码：	R-PDSO-G24	JESD-609代码：	e4
长度：	8.6487 mm	湿度敏感等级：	3
端子数量：	24	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装等效代码：	SSOP24,.24
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	电源：	3.3 V
主时钟/晶体标称频率：	100 MHz	认证状态：	Not Qualified
座面最大高度：	1.7526 mm	子类别：	Clock Generators
最大压摆率：	100 mA	最大供电电压：	3.465 V
最小供电电压：	3.135 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：	GULL WING	端子节距：	0.635 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	20
宽度：	3.8989 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：	1

W134 数据手册

W134M/W134S

W133

W158

W159

W161

W167

Refclk

Phase

PLL

Busclk

Align

CY2210

RAC

RMC

Pclk

DLL

Synclk

Gear

Ratio

Logic

Figure 1. DDLL System Architecture

face of the RAC. The DDLL together with the Gear Ratio Logic

enables users to exchange data directly from the Pclk domain

to the Synclk domain without incurring additional latency for

synchronization. In general, Pclk and Synclk can be of different

frequencies, so the Gear Ratio Logic must select the appropri-

ate M and N dividers such that the frequencies of Pclk/M and

Synclk/N are equal. In one interesting example,

Pclk=133 MHz, Synclk=100 MHz, and M=4 while N=3, giving

Pclk/M=Synclk/N=33 MHz. This example of the clock wave-

forms with the Gear Ratio Logic is shown in Figure 2.

DDLL SystemArchitectureand GearRatio Logic

Figure 1 shows the Distributed Delay Lock Loop (DDLL) sys-

tem architecture, including the main system clock source, the

Direct Rambus clock generator (DRCG), and the core logic

that contains the Rambus Access Cell (RAC), the Rambus

Memory Controller (RMC), and the Gear Ratio Logic. (This

diagram abstractly represents the differential clocks as a sin-

gle Busclk wire.)

The purpose of the DDLL is to frequency-lock and phase-align

the core logic and Rambus clocks (Pclk and Synclk) at the

RMC/RAC boundary in order to allow data transfers without

incurring additional latency. In the DDLL architecture, a PLL is

used to generate the desired Busclk frequency, while a distrib-

uted loop forms a DLL to align the phase of Pclk and Synclk at

the RMC/RAC boundary.

The output clocks from the Gear Ratio Logic, Pclk/M, and

Synclk/N, are output from the core logic and routed to the

DRCG Phase Detector inputs. The routing of Pclk/M and Syn-

clk/N must be matched in the core logic as well as on the

board.

After comparing the phase of Pclk/M vs. Synclk/N, the DRCG

Phase Detector drives a phase aligner that adjusts the phase

of the DRCG output clock, Busclk. Since everything else in the

distributed loop is fixed delay, adjusting Busclk adjusts the

phase of Synclk and thus the phase of Synclk/N. In this man-

ner the distributed loop adjusts the phase of Synclk/N to match

that of Pclk/M, nulling the phase error at the input of the DRCG

Phase Detector. When the clocks are aligned, data can be

exchanged directly from the Pclk domain to the Synclk do-

main.

The main clock source drives the system clock (Pclk) to the

core logic, and also drives the reference clock (Refclk) to the

DRCG. For typical Intel architecture platforms, Refclk will be

half the CPU front side bus frequency. A PLL inside the DRCG

multiplies Refclk to generate the desired frequency for Busclk,

and Busclk is driven through a terminated transmission line

(Rambus Channel). At the mid-point of the channel, the RAC

senses Busclk using its own DLL for clock alignment, followed

by a fixed divide-by-4 that generates Synclk.

Pclk is the clock used in the memory controller (RMC) in the

core logic, and Synclk is the clock used at the core logic inter-

Table 1 shows the combinations of Pclk and Busclk frequen-

cies of greatest interest, organized by Gear Ratio.

Pclk

Synclk

Pclk/M =

Synclk/N

Figure 2. Gear Ratio Timing Diagram

1 234 5 6 7...12

下载PDF

与W134相关器件

型号	品牌	描述	获取价格	数据表
W134H	SILICON	Direct Rambusâ¢ Clock Generator	获取价格
W134HT	SILICON	Direct Rambusâ¢ Clock Generator	获取价格
W134M	CYPRESS	Direct Rambus Clock Generator	获取价格
W134M_05	CYPRESS	Direct Rambus⑩ Clock Generator	获取价格
W134MH	CYPRESS	Direct Rambus⑩ Clock Generator	获取价格
W134MHT	CYPRESS	Direct Rambus⑩ Clock Generator	获取价格

与W134相关文章

资料手册解读：UC3842参数和管脚说明
2024-05-22

2
一文带你了解无源晶振的负载电容为何要加两颗谐振电容CL1和CL2
2024-05-22

3
玻璃管保险丝与陶瓷管保险丝：区别与替代性探讨
2024-05-22

2
PCF8574资料解读：主要参数分析、引脚说明
2024-05-21

11

产品中心

服务支持

精选活动

关于我们

帮助中心

W134

W134 技术参数

W134 数据手册

与W134相关器件

与W134相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

W134

W134 技术参数

W134 数据手册

与W134相关器件

与W134相关文章

您还可以找

您在本页遇到什么问题？