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W134

更新时间： 2024-01-19 11:52:08
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其他 - ETC 时钟
页数 文件大小 规格书
12页 188K
描述
Clocks and Buffers

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W134 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：SSOP包装说明：0.150 INCH, LEAD FREE, SSOP-24
针数：24Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.76Is Samacsys：N
JESD-30 代码：R-PDSO-G24JESD-609代码：e4
长度：8.6487 mm湿度敏感等级：3
端子数量：24最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP24,.24
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：260电源：3.3 V
主时钟/晶体标称频率：100 MHz认证状态：Not Qualified
座面最大高度：1.7526 mm子类别：Clock Generators
最大压摆率：100 mA最大供电电压：3.465 V
最小供电电压：3.135 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：20
宽度：3.8989 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：1

W134 数据手册

 浏览型号W134的Datasheet PDF文件第2页浏览型号W134的Datasheet PDF文件第3页浏览型号W134的Datasheet PDF文件第4页浏览型号W134的Datasheet PDF文件第6页浏览型号W134的Datasheet PDF文件第7页浏览型号W134的Datasheet PDF文件第8页 
W134M/W134S  
Table 3. Clock Stop Mode Selection  
Table 5. Power-down Mode Selection  
Mode  
Normal  
Clk Stop  
StopB  
Clk  
ClkB  
Mode  
Normal  
PwrDnB  
Clk  
ClkB  
PAclkB  
GND  
1
0
PAclk  
PAclkB  
1
0
PAclk  
GND  
V
V
X,STOP  
X,STOP  
Power-down  
Table 4 shows the logic for selecting the Bypass and Test  
modes. The select bits, S0 and S1, control the selection of  
these modes. The Bypass mode brings out the full-speed PLL  
output clock, bypassing the Phase Aligner. The Test mode  
brings the Refclk input all the way to the output, bypassing both  
the PLL and the Phase Aligner. In the Output Test mode (OE),  
both the Clk and ClkB outputs are put into a high-impedance  
state (Hi-Z). This can be used for component testing and for  
board-level testing.  
Table of Frequencies and Gear Ratios  
Table 6 shows several supported Pclk and Busclk frequencies,  
the corresponding A and B dividers required in the DRCG PLL,  
and the corresponding M and N dividers in the gear ratio logic.  
The column Ratio gives the Gear Ratio as defined Pclk/Synclk  
(same as M and N). The column F@PD gives the divided down  
frequency (in MHz) at the Phase Detector, where  
F@PD=Pclk/M=Synclk/N.  
Table 4. Bypass and Test Mode Selection  
Bypclk  
State Transitions  
The clock source has three fundamental operating states. Fig-  
ure 4 shows the state diagram with each transition labelled A  
through H. Note that the clock source output may NOT be  
glitch-free during state transitions.  
Mode  
S0  
S1  
(int.)  
Gnd  
-
Clk  
PAclk  
Hi-Z  
ClkB  
PAclkB  
Hi-Z  
Normal  
0
0
Output Test (OE)  
Bypass  
0
1
Upon powering up the device, the device can enter any state,  
depending on the settings of the control signals, PwrDnB and  
StopB.  
1
0
PLLclk PLLclk PLLclkB  
Refclk Refclk RefclkB  
Test  
1
1
In Power-down mode, the clock source is powered down with  
the control signal, PwrDnB, equal to 0. The control signals S0  
and S1 must be stable before power is applied to the device,  
and can only be changed in Power-down mode (PwrDnB=0).  
The reference inputs, V  
be grounded during the Power-down mode.  
Table 5 shows the logic for selecting the Power-down mode,  
using the PwrDnB input signal. PwrDnB is active LOW (en-  
abled when 0). When PwrDnB is disabled, the DRCG is in its  
normal mode. When PwrDnB is enabled, the DRCG is put into  
a powered-off state, and the Clk and ClkB outputs are three-  
stated.  
and V  
, may remain on or may  
DDR  
DDPD  
Table 6. Examples of Frequencies, Dividers, and Gear Ratios  
Pclk  
67  
Refclk  
33  
Busclk  
267  
Synclk  
67  
A
8
6
8
4
6
B
1
1
1
1
1
M
2
8
4
4
8
N
2
6
4
2
6
Ratio  
1.0  
F@PD  
33  
100  
100  
133  
133  
50  
300  
75  
1.33  
1.0  
12.5  
25  
50  
400  
100  
67  
67  
267  
2.0  
33  
67  
400  
100  
1.33  
16.7  
V
Turn-On  
M
V
Turn-On  
G
DD  
DD  
J
L
Test  
Normal  
N
B
F
K
A
E
V
Turn-On  
V
Turn-On  
DD  
D
C
DD  
Power-Down  
Clk Stop  
H
Figure 4. Clock Source State Diagram  
5
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