Datasheet > W132-09BX

W132-09BX

更新时间： 2024-02-14 06:25:58

品牌	Logo	应用领域
其他 - ETC		时钟驱动器
页数	文件大小	规格书
13页	154K
描述
Nine Distributed-Output Clock Driver

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W132-09BX 技术参数

生命周期：	Obsolete	零件包装代码：	TSSOP
包装说明：	TSSOP,	针数：	24
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.75	系列：	132
输入调节：	STANDARD	JESD-30 代码：	R-PDSO-G24
长度：	7.8 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
功能数量：	1	反相输出次数：
端子数量：	24	实输出次数：	9
最高工作温度：	70 °C	最低工作温度：
输出特性：	SERIES-RESISTOR	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.1 ns	座面最大高度：	1.1 mm
最大供电电压 (Vsup)：	3.63 V	最小供电电压 (Vsup)：	2.97 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
宽度：	4.4 mm	最小 fmax：	140 MHz
Base Number Matches：	1

W132-09BX 数据手册

W134M/W134S

W133

W158

W159

W161

W167

Refclk

Phase

PLL

Busclk

Align

CY2210

RAC

RMC

Pclk

DLL

Synclk

Gear

Ratio

Logic

Figure 1. DDLL System Architecture

face of the RAC. The DDLL together with the Gear Ratio Logic

enables users to exchange data directly from the Pclk domain

to the Synclk domain without incurring additional latency for

synchronization. In general, Pclk and Synclk can be of differ-

ent frequencies, so the Gear Ratio Logic must select the ap-

propriate M and N dividers such that the frequencies of Pclk/M

and Synclk/N are equal. In one interesting example,

Pclk = 133 MHz, Synclk = 100 MHz, and M = 4 while N = 3,

giving Pclk/M = Synclk/N = 33 MHz. This example of the clock

waveforms with the Gear Ratio Logic is shown in Figure 2.

DDLL System Architecture and Gear Ratio Log-

Figure 1 shows the Distributed Delay Lock Loop (DDLL) sys-

tem architecture, including the main system clock source, the

Direct Rambus clock generator (DRCG), and the core logic

that contains the Rambus Access Cell (RAC), the Rambus

Memory Controller (RMC), and the Gear Ratio Logic. (This

diagram abstractly represents the differential clocks as a sin-

gle Busclk wire.)

The output clocks from the Gear Ratio Logic, Pclk/M, and

Synclk/N, are output from the core logic and routed to the

DRCG Phase Detector inputs. The routing of Pclk/M and Syn-

clk/N must be matched in the core logic as well as on the

board.

The purpose of the DDLL is to frequency-lock and phase-align

the core logic and Rambus clocks (Pclk and Synclk) at the

RMC/RAC boundary in order to allow data transfers without

incurring additional latency. In the DDLL architecture, a PLL is

used to generate the desired Busclk frequency, while a distrib-

uted loop forms a DLL to align the phase of Pclk and Synclk at

the RMC/RAC boundary.

After comparing the phase of Pclk/M vs. Synclk/N, the DRCG

Phase Detector drives a phase aligner that adjusts the phase

of the DRCG output clock, Busclk. Since everything else in the

distributed loop is fixed delay, adjusting Busclk adjusts the

phase of Synclk and thus the phase of Synclk/N. In this man-

ner the distributed loop adjusts the phase of Synclk/N to match

that of Pclk/M, nulling the phase error at the input of the DRCG

Phase Detector. When the clocks are aligned, data can be

exchanged directly from the Pclk domain to the Synclk do-

main.

The main clock source drives the system clock (Pclk) to the

core logic, and also drives the reference clock (Refclk) to the

DRCG. For typical Intel architecture platforms, Refclk will be

half the CPU front side bus frequency. A PLL inside the DRCG

multiplies Refclk to generate the desired frequency for Busclk,

and Busclk is driven through a terminated transmission line

(Rambus Channel). At the mid-point of the channel, the RAC

senses Busclk using its own DLL for clock alignment, followed

by a fixed divide-by-4 that generates Synclk.

Table 1 shows the combinations of Pclk and Busclk frequen-

cies of greatest interest, organized by Gear Ratio.

Pclk is the clock used in the memory controller (RMC) in the

core logic, and Synclk is the clock used at the core logic inter-

Pclk

Synclk

Pclk/M =

Synclk/N

Figure 2. Gear Ratio Timing Diagram

Document #: 38-07426 Rev. *A

Page 3 of 13

1 234 5 6 7...13

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与W132-09BX相关器件

型号	品牌	描述	获取价格	数据表
W132-09BXT	CYPRESS	PLL Based Clock Driver, 132 Series, 9 True Output(s), 0 Inverted Output(s), PDSO24, MO-153	获取价格
W132-10	CYPRESS	Clock Driver, PDSO24,	获取价格
W132-10B	ETC	Ten Distributed-Output Clock Driver	获取价格
W132-10BX	ROCHESTER	132 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, MO-15	获取价格
W132-10BXT	ROCHESTER	132 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, MO-15	获取价格
W132XGD	KINGBRIGHT	Single Color LED, Green, Diffused, T-1, 3mm,	获取价格

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