Datasheet > W132-09B

W132-09B

更新时间： 2024-01-05 23:26:12

品牌	Logo	应用领域
其他 - ETC		时钟驱动器
页数	文件大小	规格书
13页	154K
描述
Nine Distributed-Output Clock Driver

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

W132-09B 技术参数

生命周期：	Obsolete	零件包装代码：	TSSOP
包装说明：	TSSOP,	针数：	24
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.75	系列：	132
输入调节：	STANDARD	JESD-30 代码：	R-PDSO-G24
长度：	7.8 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
功能数量：	1	反相输出次数：
端子数量：	24	实输出次数：	9
最高工作温度：	70 °C	最低工作温度：
输出特性：	SERIES-RESISTOR	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.1 ns	座面最大高度：	1.1 mm
最大供电电压 (Vsup)：	3.63 V	最小供电电压 (Vsup)：	2.97 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
宽度：	4.4 mm	最小 fmax：	140 MHz
Base Number Matches：	1

W132-09B 数据手册

W134M/W134S

Table 1. Supported Pclk and Busclk Frequencies, by Gear Ratio

Gear Ratio and Busclk

Pclk

2.0

1.5

1.33

1.0

67 MHz

267 MHz

400 MHz

100 MHz

133 MHz

150 MHz

200 MHz

300 MHz

400 MHz

267 MHz

400 MHz

356 MHz

400 MHz

StopB

S0/S1

W134M/W134S

W133

W158

W159

W161

W167

Refclk

Phase

PLL

Busclk

Align

CY2210

RAC

RMC

Pclk

DLL

Synclk

Gear

Ratio

Logic

Figure 3. DDLL Including Details of DRCG

Figure 3 shows more details of the DDLL system architecture,

including the DRCG output enable and bypass modes.

directly, by bypassing the Phase Aligner. If PclkM and SynclkN

are not used, those inputs must be grounded.

Phase Detector Signals

Selection Logic

The DRCG Phase Detector receives two inputs from the core

logic, PclkM (Pclk/M) and SynclkN (Synclk/N). The M and N

dividers in the core logic are chosen so that the frequencies of

PclkM and SynclkN are identical. The Phase Detector detects

the phase difference between the two input clocks, and drives

the DRCG Phase Aligner to null the input phase error through

the distributed loop. When the loop is locked, the input phase

error between PclkM and SynclkN is within the specification

t_ERR,PDgiven in Table 14 after the lock time given in the State

Transition Section.

Table 2 shows the logic for selecting the PLL prescaler and

feedback dividers to determine the multiply ratio for the PLL

from the input Refclk. Divider A sets the feedback and divider

B sets the prescaler, so the PLL output clock frequency is set

by: PLLclk=Refclk*A/B.

Table 2. PLL Divider Selection

W134M

W134S

Mult0

Mult1

The Phase Detector aligns the rising edge of PclkM to the

rising edge of SynclkN. The duty cycle of the phase detector

input clocks will be within the specification DC_IN,PDgiven in

Table 13. Because the duty cycles of the two phase detector

input clocks will not necessarily be identical, the falling edges

of PclkM and SynclkN may not be aligned when the rising edg-

es are aligned.

Table 3 shows the logic for enabling the clock outputs, using

the StopB input signal. When StopB is HIGH, the DRCG is in

its normal mode, and Clk and ClkB are complementary outputs

following the Phase Aligner output (PAclk). When StopB is

LOW, the DRCG is in the Clk Stop mode, the output clock

drivers are disabled (set to Hi-Z), and the Clk and ClkB settle

to the DC voltage V_X,STOPas given in Table 14. The level of

V_X,STOPis set by an external resistor network.

The voltage levels of the PclkM and SynclkN signals are de-

termined by the controller. The pin VDDIPD is used as the

voltage reference for the phase detector inputs and should be

connected to the output voltage supply of the controller. In

some applications, the DRCG PLL output clock will be used

Document #: 38-07426 Rev. *A

Page 4 of 13

1 2 345 6 7...13

下载PDF

与W132-09B相关器件

型号	品牌	描述	获取价格	数据表
W132-09BX	ETC	Nine Distributed-Output Clock Driver	获取价格
W132-09BXT	CYPRESS	PLL Based Clock Driver, 132 Series, 9 True Output(s), 0 Inverted Output(s), PDSO24, MO-153	获取价格
W132-10	CYPRESS	Clock Driver, PDSO24,	获取价格
W132-10B	ETC	Ten Distributed-Output Clock Driver	获取价格
W132-10BX	ROCHESTER	132 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, MO-15	获取价格
W132-10BXT	ROCHESTER	132 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, MO-15	获取价格

与W132-09B相关文章

资料手册解读：UC3842参数和管脚说明
2024-05-22

3
一文带你了解无源晶振的负载电容为何要加两颗谐振电容CL1和CL2
2024-05-22

4
玻璃管保险丝与陶瓷管保险丝：区别与替代性探讨
2024-05-22

2
PCF8574资料解读：主要参数分析、引脚说明
2024-05-21

11

产品中心

服务支持

精选活动

关于我们

帮助中心

W132-09B

W132-09B 技术参数

W132-09B 数据手册

与W132-09B相关器件

与W132-09B相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

W132-09B

W132-09B 技术参数

W132-09B 数据手册

与W132-09B相关器件

与W132-09B相关文章

您还可以找

您在本页遇到什么问题？