Datasheet > VSC9180UV

VSC9180UV

更新时间： 2024-02-12 12:16:56

品牌	Logo	应用领域
美高森美 - MICROSEMI		/
页数	文件大小	规格书
28页	499K
描述
Telecom IC,

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VSC9180UV 技术参数

生命周期：	Transferred	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.82

VSC9180UV 数据手册

VSC9180

Data Sheet

Functional Overview

The VSC9180 Hitless Transceiver receives parallel data on a 4-bit or 16-bit bus and serializes it to redundant 2.5Gb/s

STS-48/STM-16 ‘like’ signal. The parallel data can be in the form of a 4-bit or 16-bit byte interleaved STS-48/STM-

16 SONET/SDH signal with an accompanying word clock, much like a traditional SONET/SDH transceiver like the

VSC8141 16-bit transceiver or VSC8144 4-bit transceiver. This data can also be four, frequency and nearly frame

synchronous, serial STS-12/STM-4 signals with no accompanying clock. In the quad serial STS-12/STM-4 mode, the

VSC9180 retimes the incoming STS-12/STM-4 signals using a reference clock, and deskews them up to +/- 3 bytes.

The four STS-12/STM-4 signals are interleaved according to the SONET/SDH sequence and STS-48 ‘like’ signal is

created. The bytes are derived directly from the four received STS-12/STM-4 signals, in groups of four per signal

channel, and no overwriting is performed on the A1/A2 boundary, B2 bytes, and K1/K2 protection. This allows the

four received tributaries to be transported transparently across the backplane.

The receive circuitry interfaces to two frequency synchronous serial STS-48 ‘like’ signals using two redundant

CDRs. The CDRs lock to their respective channels, recover the clocks, and deserialize each signal internally. Both

signals are then framed and dual FIFOs are used to deskew both signals by up to +/-75ns. Once this deskew has been

performed, the CHSEL signal allows the user to choose which received input is then de-multiplexed to the parallel

output. Loss of Lock (LOL), Severely Errored Frame (SEF), and Bit Error Rate (BER) alarms are provided on a per

channel basis. SEF and BER can be used to drive the CHSEL signal so a 'hitless' transition will take place in hard-

ware if the selected input fails for external reasons. LOL is not recommended for this if there is a possibility of one of

the input channels becoming disconnected. Per channel bit error rate (BER) alarms provide additional information for

controlling CHSEL. A Loss of Alignment (LOA) alarm is provided to indicate that the received signals are either

non-synchronous or are skewed beyond the capability of the VSC9180 to hitlessly switch. The INTRLV and BUS-

MODE signals select the mode to recreate either the 4-bit or 16-bit byte interleaved STS-48/STM-16 output, or the

original received STS-12/STM-4 signals.

Figure 1: Hitless Backplane Sparing in Synchronous TSI/ADM Applications

Protection

VSC8144

VSC9180

'Hitless'

Xceiver

Pointer Processor

Performance Monitor

FEC CODEC

2.5G SDH

Interface

2.5G

4-bit

Backplane

Interface

SONET

Xceiver

Working

System Timing Domain

Line Timing Domain

The CDR circuitry recovers the incoming clock using the same reference provided to the CMU on the transmit side.

The received signal frequency does not need to exactly match the transmitted signal frequency allowing the device to

be used in wavelength cross connect applications where the bidirectional signals will be different frequencies. The

VSC9180 supports both line and equipment loopback, though not both simultaneously.

3 of 28

G52346, Revision 4.6

September 2, 2003

1 234 5 6 7...28

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与VSC9180UV相关器件

型号	品牌	获取价格	描述	数据表
VSC9182	VITESSE	获取价格	VSC9182 - 40G STS-1 Time Slot Interchange
VSC9182UG	VITESSE	获取价格	TELECOM, DIGITAL TIME SWITCH, PBGA480, 37.50 MM, HEAT SINK, TBGA-480
VSC9182-UG	MICROSEMI	获取价格	Digital Time Switch, PBGA480, TBGA-480
VSC9182XX	VITESSE	获取价格	Digital Time Switch, PBGA480, 37.50 MM, TBGA-480
VSC9186	VITESSE	获取价格	VSC9186 Killington - Quad STS-48/STM-16 and STS-192/STM-64 Line Interface
VSC9187	VITESSE	获取价格	VSC9187 Bromley - 3045 x 3045 VT1.5 TSI Switch Fabric
VSC9188	MICROSEMI	获取价格	Micro Peripheral IC,
VSC9188	VITESSE	获取价格	Micro Peripheral IC,
VSC9190	VITESSE	获取价格	Telecom IC
VSC9191	VITESSE	获取价格	100 Gbps (40 x 40) SONET/SDH TSI Switch with Dual Rate I/O

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