Datasheet > VSC9180UV

VSC9180UV

更新时间： 2024-01-06 00:44:43

品牌	Logo	应用领域
美高森美 - MICROSEMI		/
页数	文件大小	规格书
28页	499K
描述
Telecom IC,

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技术参数
数据手册

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VSC9180UV 技术参数

生命周期：	Transferred	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.82

VSC9180UV 数据手册

VSC9180

Data Sheet

Features Summary

Parallel to Serial Transmit Features

• Receives 16- or 4-bit parallel LVDS inputs operating at 155MHz or 622MHz, respectively, into an internal

FIFO using source synchronous timing

• 16-bit 155MHz bus or 4-bit 622MHz bus is bit multiplexed to serial 2.5GHz output

• Retimes four serial STS-12/STM-4 inputs and deskews up to +/- 3 bytes of skew using the A1/A2 bound-

aries

• Byte interleaves four serial STS-12/STM-4 inputs to create an STS-48 like signal

• Supports bit multiplexing at 2.488GHz, and 2.65GHz

Serial to Parallel Receive Features

• Dual 2.5Gb/s frequency synchronous serial CML inputs with onboard clock and data recovery

• On-board frame alignment of received signals and large internal FIFO for tolerance of up to +/- 75ns of

serial backplane skew

• Realignment of incoming signals allows hitless selection of incoming channel for maintenance purposes,

and prevents downstream devices from having to reframe in a failure condition

• Supports bit de-multiplexing at 2.488GHz and 2.65GHz

• Hardware based switch over within receipt of two or four errored frame boundaries

• Loss of lock, loss of alignment, and loss of frame alarm indication

• Receive BER monitoring with selectable error thresholds

• Received frame pointer output for SYNC distribution

• Returns 16 or 4 bit parallel LVDS bit demultiplexed outputs operating at 155MHz or 622MHz with recov-

ered bus clock

• Returns four serial STS-12/STM-4 outputs to same signal pins as received by multiplexer for transparent

STS-12/STM-4 backplane transport

Other Features

• 4-bit or 16-bit parallel bus loopback with output bus clock

• Parallel loopback also allows quad STS-12/STM-4 retime, realign, and loopback output

• Serial loopback with hitless input selection and realignment

• Onboard discrete CMU and CRU to accommodate non-synchronous TX/RX applications

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G52346, Revision 4.6

September 2, 2003

123 4 5 6 7...28

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