VSC8211
Datasheet
Figures
Figure 1. Parallel MAC to Cat-5, Fiber Optics, or Backplanes.............................................................................. 3
Figure 2. Serial MAC to Cat-5, Fiber Optics, or Backplanes ................................................................................ 3
Figure 3. GBIC/SFP Serial Interface (SGMII or 802.3z SerDes to Cat-5) ............................................................ 3
Figure 4. Media Converter (1000BASE-X to Cat-5).............................................................................................. 4
Figure 5. VSC8211 Block Diagram ..................................................................................................................... 17
Figure 6. VSC8211 117 Ball LBGA Package Ball Diagram................................................................................. 18
Figure 7. 117-Ball LBGA Signal Map (top view).................................................................................................. 19
Figure 8. System Schematic - ‘Parallel Data MAC to CAT5 Media’ PHY Operating Mode................................. 36
Figure 9. System Schematic - ‘Parallel Data MAC to 1000Mbps Fiber Media’ PHY Operating Mode................ 37
Figure 10. System Schematic - ‘Parallel Data MAC to Copper/Fiber Auto Media Sense’ PHY Operating Mode. 38
Figure 11. System Schematic - ‘SGMII/802.3z SerDes MAC to CAT5 Media’ PHY Operating Mode .................. 39
Figure 12. System Schematic - ‘SGMII/802.3z SerDes to 1000Mbps Fiber Media’ PHY Operating Mode .......... 40
Figure 13. System Schematic – ‘100Mbps Fiber Media’ Implementation............................................................. 41
Figure 14. System Schematic - ‘Serial MAC to Fiber/CAT5 Media' PHY Operating Mode................................... 42
Figure 15. VSC8211 Twisted Pair Interface.......................................................................................................... 43
Figure 16. Data Validity......................................................................................................................................... 46
Figure 17. Start [S] and Stop [T] Definition ........................................................................................................... 47
Figure 18. Acknowledge (By Receiver) [A]........................................................................................................... 47
Figure 19. Acknowledge (By Host) [H].................................................................................................................. 47
Figure 20. No Acknowledge (By Host) [N]............................................................................................................ 47
Figure 21. Random Write...................................................................................................................................... 48
Figure 22. Sequential Write .................................................................................................................................. 49
Figure 23. Random Read ..................................................................................................................................... 50
Figure 24. Sequential Read.................................................................................................................................. 51
Figure 25. MDIO Read Frame .............................................................................................................................. 53
Figure 26. MDIO Write Frame............................................................................................................................... 53
Figure 27. Logical Representation of MDINT Pin ................................................................................................. 53
Figure 28. Test Access Port and Boundary Scan Architecture............................................................................. 57
Figure 29. Enhanced ActiPHY State Diagram ...................................................................................................... 60
Figure 30. In-line Powered Ethernet Switch Diagram........................................................................................... 62
Figure 31. Far-end Loopback Block Diagram....................................................................................................... 64
Figure 32. Near-end Loopback Block Diagram..................................................................................................... 65
Figure 33. Connector Loopback Block Diagram................................................................................................... 65
Figure 34. EEPROM Interface Connections......................................................................................................... 73
Figure 35. PHY Startup and Initialization Sequence............................................................................................. 75
Figure 36. Extended Page Register Diagram....................................................................................................... 80
Figure 37. GMII Transmit AC Timing in 1000BASE-T Mode................................................................................ 145
Figure 38. GMII Receive AC Timing in 1000BASE-T Mode ............................................................................... 146
Figure 39. MII Transmit AC Timing (100Mbps)................................................................................................... 147
Figure 40. MII Receive AC Timing (100Mbps).................................................................................................... 147
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VMDS-10105 Revision 4.1
October 2006
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