Datasheet > VSC7216XUI-06

VSC7216XUI-06

更新时间： 2024-02-17 05:27:00

品牌	Logo	应用领域
VITESSE		/
页数	文件大小	规格书
40页	793K
描述
Telecom IC, PBGA256

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技术参数
数据手册

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VSC7216XUI-06 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	BGA, BGA256,20X20,50	Reach Compliance Code：	unknown
风险等级：	5.7	JESD-30 代码：	S-PBGA-B256
端子数量：	256	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA256,20X20,50
封装形状：	SQUARE	封装形式：	GRID ARRAY
电源：	2.5 V	认证状态：	Not Qualified
子类别：	Other Telecom ICs	最大压摆率：	335 mA
标称供电电压：	2.5 V	表面贴装：	YES
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	Base Number Matches：	1

VSC7216XUI-06 数据手册

VSC7216-06

Data Sheet

Word Sync Generation

The VSC7216-06 can perform channel alignment (also referred to as “word alignment” or “word sync”), meaning

that the four receive data output streams are aligned such that the same 4-byte word presented to the four transmit

channel inputs for serialization will be transferred on the receive channel parallel outputs. The Word Sync Sequence

provides a unique synchronization point in the serial data stream that is used to align the receive channels. This

sequence consists of 16 consecutive K28.5 IDLE characters with disparity reversals on the second and fourth

characters. The Word Sync Sequence is sent either as I+ I+ I- I- I+ I- I+ I- I+ I- I+ I- I+ I- I+ I- or as I- I- I+ I+ I- I+ I-

I+ I- I+ I- I+ I- I+ I- I+, depending on the transmitter’s running disparity at the time the first IDLE character is

serialized.

Transmission of the Word Sync Sequence is initiated independently in each channel when the WSENn input is

asserted HIGH for one character time (see Figure 5). When WSENn is HIGH, the C/Dn and Tn[7:0] inputs are

ignored. The WSENn, C/Dn and Tn[7:0] inputs are also ignored for the subsequent 15 character times. The Word

Sync Sequence, shown in Figure 5, is initiated in cycle W1 and transmitted through cycle W16. Normal data

transmission (or the transmission of another Word Sync Sequence) resumes in cycle D3. This figure is drawn

assuming that input timing is referenced to REFCLK (for example, TMODE[2:0] = 000) with the DUAL input LOW.

As long as WSENn remains asserted, another Word Sync Sequence will be generated.

W9 W10 W11 W12 W13 W14 W15 W16 D3

REFCLK

WSENn

C/Dn

Tn[7:0]

0x01 0x02 XX

XX 0x03 0x04

TXn+/-

D1.0+ D2.0+ K28.5+ K28.5+ K28.5- K28.5- K28.5+ K28.5- K28.5+ K28.5- K28.5+ K28.5- K28.5+ K28.5- K28.5+ K28.5- K28.5+ K28.5- D3.0+ D4.0-

Figure 5. Word Sync Sequence Generation

Serializer

The 10-bit output from the encoder (or from the encoder input register if ENDEC is LOW) is fed into a multiplexer

that serializes the parallel data using the synthesized transmit clock. The least significant bit of the 10B data is

transmitted first. Each channel has both primary and redundant serial output ports, PTXn and RTXn respectively,

which consist of differential PECL output buffers operating at either 10 or 20 times the REFCLK rate. The primary

and redundant transmitter outputs are separately controllable on each channel. The primary PECL outputs PTXn are

enabled when the PTXENn input is HIGH, and the redundant PECL outputs RTXn are enabled when the RTXENn

input is HIGH. When a PECL output is disabled, the associated output buffers do not consume power and the attached

pins are undriven.

7 of 40

G52416, Revision 4.0

December 2006

1...4 5 678 9 10...40

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与VSC7216XUI-06相关器件

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VSC7217	VITESSE	Multi-Gigabit Interconnect Chip	获取价格
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VSC7226	VITESSE	Quad 3.125Gb/s Backplane Transceiver	获取价格
VSC7226-01	MICROSEMI	Ethernet Transceiver, PBGA256, 21 MM, BGA-256	获取价格
VSC7226-02	MICROSEMI	Ethernet Transceiver, PBGA256, 21 MM, BGA-256	获取价格
VSC7226UC-01	MICROSEMI	Telecom IC,	获取价格

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