VSC7123XQN

更新时间： 2024-02-11 02:09:16

品牌	Logo	应用领域
VITESSE		光纤以太网
页数	文件大小	规格书
18页	210K
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数据手册

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VSC7123XQN 数据手册

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

10-Bit Transceiver for Fibre

Channel and Gigabit Ethernet

VSC7123

Figure 4: Transmit Timing Waveforms

REFCLK

T(0:9)

T₂

T₁

Data Valid

Table 2: Transmit AC Characteristics

Parameters

Description

Min

Typ

Max Units

Conditions

Measured between the valid data

level of T(0:9) to the 1.4V point

of REFCLK.

T(0:9) Setup time to the rising

edge of REFCLK

T₁

1.5

—

T(0:9) hold time after the rising

edge of REFCLK

T₂

1.0

—

20% to 80%, 50Ω load to

V_DD-2.0.

_SDR,T_SDF

TX+/TX- rise and fall time

—

300

Latency from rising edge of

REFCLK to T0 appearing on

TX+/TX-

8bc+

4ns

bc = Bit clocks

ns = Nano second

T_LAT

8bc

—

Transmitter Output Jitter Allocation

Measured at SO+/-, 1 sigma

deviation of 50% crossing point.

Random jitter (RMS)

—

ps.

Serial data output deterministic

jitter (pk-pk)

IEEE 802.3Z Clause 38.68,

tested on a sample basis.

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Page 6

G52212-0, Rev 4.3

03/25/01

1...3 4 567 8 9...18

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