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VSC7123XYW PDF预览

VSC7123XYW

更新时间: 2024-01-24 14:40:29
品牌 Logo 应用领域
VITESSE /
页数 文件大小 规格书
22页 467K
描述
Telecom IC, PQFP64

VSC7123XYW 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:QFP, TQFP64,.63SQ,32Reach Compliance Code:unknown
风险等级:5.84JESD-30 代码:S-PQFP-G64
端子数量:64封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:TQFP64,.63SQ,32
封装形状:SQUARE封装形式:FLATPACK
电源:3.3 V认证状态:Not Qualified
子类别:Other Telecom ICs最大压摆率:260 mA
标称供电电压:3.3 V表面贴装:YES
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUADBase Number Matches:1

VSC7123XYW 数据手册

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VSC7123  
Datasheet  
10-Bit Transceiver for Fibre Channel and Gigabit Ethernet  
Features  
Automatic lock-to-reference  
RX cable equalization  
802.3z Gigabit Ethernet-compliant  
1.25 Gbps transceiver  
Analog and digital signal detection  
JTAG access port for testability  
Single +3.3 V supply, 650 mW typical  
ANSI X3T11 Fibre Channel-compliant  
1.0625 Gbps transceiver  
0.98 to 1.36 Gbps full-duplex operation  
10-Bit TTL interface for transmit and receive data  
Packages: 64-pin 10 mm and 14 mm QFP and  
10 mm and 14 mm TQFP  
General Description  
The VSC7123 is a full-speed Fibre Channel and Gigabit Ethernet transceiver with industry-standard pinouts. The  
VSC7123 accepts 10-bit 8B/10B encoded transmit data, latches it on the rising edge of REFCLK and serializes the  
data onto the TX PECL differential outputs at a baud rate, which is 10 times the REFCLK frequency. Serial data input  
on the RX PECL differential inputs is resampled by the Clock Recovery Unit (CRU) and deserialized onto the 10-bit  
receive data bus synchronously to complementary divide-by-twenty clocks. The VSC7123 receiver detects “Comma”  
characters for frame alignment. An analog/digital signal detection circuit indicates that a valid signal is present on the  
RX input. A cable equalizer compensates for InterSymbol Interference (ISI) to increase maximum cable distances.  
The VSC7123 is a higher performance, lower cost replacement for the VSC7125 and VSC7135.  
Block Diagram  
10  
Serial to  
Parallel  
Q D  
Q D  
R(0:9)  
Q
D
RX+  
RX-  
2:1  
÷10  
÷20  
Clock  
Recovery  
RCLK  
RCLKN  
Comma  
Detect  
COMDET  
ENCDET  
EWRAP  
Signal  
Detect  
SIGDET  
10  
TX+  
TX-  
Parallel  
to Serial  
T(0:9)  
D Q  
D Q  
x10 Clock  
Multiply  
REFCLK  
NOT SHOWN: JTAG Boundary Scan  
G52212-0 Revision 4.7  
March 14, 2008  
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012  
Tel: (800) VITESSE • FAX: (805) 987-5896 • E-mail: webmaster@vitesse.com  
Internet: www.vitesse.com  
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