D3 Test Enable: Writing “1” to D3 of Test Register at 0Ch, initiates a BIT test that disconnects all channels from
the outside world and connects them across an internal stimulus that generates and tests 72 different angles to a
test accuracy of 0.05°. External reference is not required. Test cycle is completed within 45 seconds and results
can be read from the Status Registers. D3 changes from “1” to “0” when test is complete. A failure will trigger an
Interrupt (if enabled). The testing requires no external programming, and can be initiated by writing "1" at D3 or
terminated by writing "0" at D3.
D0 Test Enable: Checks card and VME interface. Writing “1” to D0 of Test Register at 0Ch disconnects all
channels from the outside world, enabling user to write any number of angles to the card at 34h. Data is then read
from the VME interface (after writing, allow 400 ms before reading). Test accuracy to be <.05°. Disable by setting
D0 to “0”. Upon writing “1”, the default test angle of D0 is 30°. External reference is not required. (ex.
330°=1110101010101011).
Status, Test: Check the corresponding bit of the Test Status Register at 46h, for status of BIT testing for each
active channel. A ”1” means Accuracy OK; “0” means failed. (test cycle takes 45 seconds for accuracy error).
Status, Ref: Check the corresponding bit of the Ref Status Register at 1Ah, for status of the reference input for
each active channel. A ”1” =Ref. ON, “0” = Ref. Loss. (Reference loss is detected after 2 seconds).
Status, Sig: Check the corresponding bit of the Sig Status Register at 0Eh, for status of the input signals for each
active channel. A "1" = Signal ON, “0” = Signal loss. (Signal loss is detected after 2 seconds).
Interrupt: Enter requirements into 4Eh as an 8-bit binary number. 0= no interrupt; 1-7 indicates priority levels.
Any error will latch Status Register and trigger an Interrupt. When Interrupt is acknowledged, additional errors will
set another Interrupt. Reading will unlatch registers. Now, let us consider what happens when a status bit changes
before registers are read. For example, if a reference loss was detected and latched into registers and subsequent
scans find that the reference was reconnected, then this status change will be held in background until registers are
read. Within 250ms registers will be updated with the background data. Allow 250 ms to scan all channels.
Interrupt Vector 1: Write 8-bit word (0-255). Used for failure reports.
Interrupt Vector 2: Write 8-bit word (0-255). Used for angle change alert reports.
Angle Change Alert: Write a 16-bit word to each channel, to represent the minimum differential required.
MSB=180°; minimum differential is 0.05°. Setting to zero disables the Angle Change Alert for a given channel.
Initiate monitoring by writing “1” to Angle Change Initiate Register at 94h. When that differential is exceeded, on
any monitored channel, an interrupt is generated. Read Angle Change Alert Flag Register at 96h for status of each
channel ("0" = no change, "1" = change)
Soft Reset: (Level sensitive): Writing a “1” to FEh initiates and holds software in reset state. Then, writing “0”
initiates reboot (takes 400 ms). Status Registers cleared; Watchdog Timer functional; Failure bit at "0"; Saved
parameters remain saved; Angle outputs held at last update; Interrupts disabled.
Watchdog Timer: This feature monitors the Watchdog Timer Register (FCh). When it detects that a code has
been received, that code will be inverted within 100 µSec. The inverted code stays in the register until replaced by a
new code. User, after 100 µSec, should look for the inverted code to confirm that the processor is operating.
Optional Reference Supply: For frequency, write a 16-bit word (Ex: 400 Hz = 1 1001 0000) to address 3A. For
voltage, write a word (Ex: 26.1 Vrms =1 0000 0101) with LSB=0.1 Vrms, to address 3C. It is recommended that
user program the required frequency before setting the output voltage.
Optional (A&B) Encoder Resolution: Enter required resolution, for each channel, per above table. Can be
changed on the fly. Also set corresponding [(A&B) or A, B, C] register to “0”. Encoder/Commutation outputs are
optional, see part ordering information. Default is 12-bit encoder mode.
Optional Commutation Outputs (A,B,C): Set channels that should produce commutation outputs to “1” in the
appropriate [(A&B) or A, B, C] register. Then, set the required motor poles (per above table) in the equivalent
(A&B) resolution registers. Encoder/Commutation outputs are optional, see part ordering information.
Serial Number: At 40h, is read as a 16-bit binary word.
Date Code: Read as a decimal number at 42h. The four digits represent YYWW (Year,Year,Week.Week)
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Rev: At 44h.
Apex Signal, A Division of NAI, Inc.
170 Wilbur Place, Bohemia, NY, 11716,USA
631.567.1100/631.567.1823(fax)
www.naii.com / e-mail:sales@naii.com
2-05-01
Code:OVGU1
S 64 SD1 A001 REV A 1.4
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