where fFS is the full scale output frequency in Hz. The
temperature drift of C1 is critical since it will add directly to
the errors of the transfer function. An NPO ceramic type is
recommended. Every effort should be made to minimize
stray capacitance associated with C1. It should be mounted
as close to the VFC320 as possible. Figure 8 shows pulse
width and full scale frequency for various values of C1 at
DFS = 25%.
OFFSET AND GAIN ADJUSTMENT PROCEDURES
To null errors to zero, follow this procedure:
1. Apply an input voltage that should produce an output
frequency of 0.001 • full scale.
2. Adjust R5 for proper output.
3. Apply the full scale input voltage.
4. Adjust R3 for proper output.
5. Repeat stems 1 through 4.
If nulling is unnecessary for the application, delete R4 and
R5, and replace R3 with a short circuit.
10,000
1000
100
106
105
104
Full Scale Frequency
POWER SUPPLY CONSIDERATIONS
The power supply rejection ratio of the VFC320 is 0.015%
of FSR/% max. To maintain ±0.015% conversion, power
supplies which are stable to within ±1% are recommended.
These supplies should be bypassed as close as possible to the
converter with 0.01µF capacitors.
Pulse Width
10
1
103
102
Internal circuitry causes some current to flow in the common
connection (pin 11 on DIP package). Current flowing into
the fOUT pin (logic sink current) will also contribute to this
current. It is advisable to separate this common lead ground
from the analog ground associated with the integrator input
to avoid errors produced by these currents flowing through
any ground return impedance.
101
102
103
104
105
Capacitance C1(pF)
FIGURE 8. Output Pulse Width (DFS = 0.25) and Full Scale
Frequency vs External One-shot Capacitance.
Integrating Capacitor, C2
DESIGN EXAMPLE
Since C2 does not occur in the V/F transfer function equation
(9), its tolerance and temperature stability are not important;
however, leakage current in C2 causes a gain error. A
ceramic type is sufficient for most applications. The value of
C2 determines the amplitude of VOUT. Input amplifier satu-
ration, noise levels for the comparators and slew rate limit-
ing of the integrator determine a range of acceptable values,
Given a full scale input of +10V, select the values of R1, R2,
R3, C1, and C2 for a 25% duty cycle at 100kHz maximum
operation into one TTL load. See Figure 6.
Selecting C1 (DFS = 0.25)
C1 = [(33 • 106)/fMAX] – 15
[(66 • 106)/fMAX] – 15
if DFS = 0.5
100/fFS; if fFS ≤ 100kHz
C2 (µF) = 0.001; if 100kHz < fFS ≤ 500kHz
0.0005; if fFS > 500kHz
(13)
= [(33 • 106)/100kHz] – 15
= 315pF
Choose a 300pF NPO ceramic capacitor with 1% to 10%
tolerance.
Output Pull Up Resistor R2
The open collector output can sink up to 8mA and still be
TTL-compatible. Select R2 according to this equation:
Selecting R1 and R3 (DRS = 0.25)
R2 min (Ω) VPULLUP/(8mA – ILOAD
)
R1 + R3 = VIN max/0.25mA
VIN max/0.5mA
if DFS = 0.5
A 10% carbon film resistor is suitable for use as R2.
= 10V/0.25mA
Trimming Components R3, R4, R5
= 40kΩ
R5 nulls the offset voltage of the input amplifier. It should
have a series resistance between 10kΩ and 100kΩ and a
temperature coefficient less than 100ppm/°C. R4 can be a
10% carbon film resistor with a value of 10MΩ.
Choose 32.4kΩ metal film resistor with 1% tolerance and
R3 = 10kΩ cermet potentiometer.
R3 nulls the gain errors of the converter and compensates for
initial tolerances of R1 and C1. Its total resistance should be
at least 20% of R1, if R1 is selected 10% low. Its temperature
coefficient should be no greater than five times that of R1 to
maintain a low drift of the R3 - R1 series combination.
Selecting C2
C2 = 102/FMAX
= 102/100kHz
= 0.001µF
Choose a 0.001µF capacitor with ±5% tolerance.
VFC320
SBVS017A
7
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