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VFC320BP/2K5

更新时间： 2024-01-04 00:17:39
品牌 Logo 应用领域
德州仪器 - TI 光电二极管转换器
页数 文件大小 规格书
12页 230K
描述
IC,VOLTAGE-TO-FREQUENCY CONVERTER,DIP,14PIN

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VFC320BP/2K5 技术参数

生命周期：Obsolete包装说明：DIP, DIP14,.3
Reach Compliance Code：unknown风险等级：5.84
转换器类型：VOLTAGE TO FREQUENCY CONVERTERJESD-30 代码：R-PDIP-T14
标称负供电电压：-15 V端子数量：14
最高工作温度：85 °C最低工作温度：-25 °C
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP14,.3封装形状：RECTANGULAR
封装形式：IN-LINE电源：+-15 V
认证状态：Not Qualified子类别：Analog Special Function Converters
最大压摆率：7.5 mA标称供电电压：15 V
表面贴装：NO温度等级：OTHER
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUALBase Number Matches：1

VFC320BP/2K5 数据手册

 浏览型号VFC320BP/2K5的Datasheet PDF文件第1页浏览型号VFC320BP/2K5的Datasheet PDF文件第2页浏览型号VFC320BP/2K5的Datasheet PDF文件第3页浏览型号VFC320BP/2K5的Datasheet PDF文件第5页浏览型号VFC320BP/2K5的Datasheet PDF文件第6页浏览型号VFC320BP/2K5的Datasheet PDF文件第7页 
FREQUENCY STABILITY VS TEMPERATURE  
DISCUSSION OF  
SPECIFICATIONS  
LINEARITY  
The full scale frequency drift of the VFC320 versus tem-  
perature is expressed as parts per million of full scale range  
per °C. As shown in Figure 3, the drift increases above  
10kHz. To determine the total accuracy drift over tempera-  
ture, the drift coefficients of external components (espe-  
cially R1 and C1) must be added to the drift of the VFC320.  
Linearity is the maximum deviation of the actual transfer  
function from a straight line drawn between the end points  
(100% full scale input or frequency and 0.1% of full scale  
called zero.) Linearity is the most demanding measure of  
voltage-to-frequency converter performance, and is a func-  
tion of the full scale frequency. Refer to Figure 1 to deter-  
mine typical linearity error for your application. Once the  
full scale frequency is chosen, the linearity is a function of  
operating frequency as it varies between zero and full scale.  
Examples for 10kHz full scale are shown in Figure 2. Best  
linearity is achieved at lower gains (∆fOUT/∆VIN) with opera-  
tion as close to the chosen full scale frequency as possible  
1000  
100  
B and S Grades  
The high linearity of the VFC320 makes the device an  
excellent choice for use as the front end of Analog-to-Digital  
(A/D) converters with 12- to 14-bit resolution, and for  
highly accurate transfer of analog data over long lines in  
noisy environments (2-wire digital transmission.)  
C Grade  
10  
1k  
10k  
100k  
1M  
Full Scale Frequency (Hz)  
Figure 3. Full Scale Drift vs Full Scale Frequency.  
0.10  
RESPONSE  
Response of the VFC320 to changes in input signal level is  
specified for a full scale step, and is 50ns plus 1 pulse of the  
new frequency. For a 10V input signal step with the VFC320  
operating at 100kHz full scale, the settling time to within  
±0.01% of full scale is 10µs.  
0.01  
TA = +25°C  
DFS = 0.25  
THEORY OF OPERATION  
0.001  
1k  
10k  
100k  
1M  
The VFC320 monolithic voltage-to-frequency converter pro-  
vides a digital pulse train output whose repetition rate is  
directly proportional to the analog input voltage. The circuit  
shown in Figure 4 is composed of an input amplifier, two  
comparators and a flip-flop (forming a on-shot), two switched  
current sinks, and an open collector output transistor stage.  
Essentially the input amplifier acts as an integrator that  
produces a two-part ramp. The first part is a function of the  
input voltage, and the second part is dependent on the input  
voltage and current sink. When a positive input voltage is  
applied at VIN, a current will flow through the input resistor,  
causing the voltage at VOUT to ramp down toward zero,  
according to dV/dt = VIN/R1C1. During this time the con-  
stant current sink is disabled by the switch. Note, this period  
is only dependent on VIN and the integrating components.  
Full Scale Frequency (Hz)  
Figure 1. Linearity Error vs Full Scale Frequency.  
Figure  
0.003  
fFULL SCALE = 10kHz  
0.002  
0.001  
0
B Grade  
C Grade  
–0.001  
–0.002  
–0.003  
Typical, TA = +25°C  
When the ramp reaches a voltage close to zero, comparator  
A sets the flip-flop. This closes the current sink switches as  
well as changing fOUT from logic 0 to logic 1. The ramp now  
0
1k  
2k  
3k  
4k  
5k  
6k  
7k  
8k  
9k 10k  
Operating Frequency (Hz)  
begins to ramp up, and 1mA charges through C1 until VC1  
=
–7.5V. Note this ramp period is dependent on the 1mA  
current sink, connected to the negative input of the op amp,  
as well as the input voltage. At this –7.5V threshold point  
C1, comparator B resets the flip-flop, and the ramp voltage  
Figure 2. Linearity Error vs Operating Frequency.  
Figure  
VFC320  
4
SBVS017A  
1234567...12

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