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USD134

更新时间： 2022-09-15 09:40:35

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
11页	145K
描述
0.35 um ULC Series with Embedded DPRAM

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Features

• High-performance ULC Family Suitable for Large-sized CPLDs and FPGAs

• From 46K Gates up to 780K Gates Supported

• From 18 Kbit to 390 Kbit DPRAM

• Compatible with Xilinx or Altera

• Pin-counts to Over 976 pins

• Any Pin–out Matched

• Full Range of Packages: DIP, SOIC, LCC/PLCC, PQFP/TQFP, BGA, PGA/PPGA

• Low Quiescent Current: 0.3 nA/gate

• Available in Commercial and Industrial Grades

• 0.35 µm Drawn CMOS, 3 and 4 Metal Layers

• Library Optimised for Synthesis, Floor Plan & Testability

Generation (ATPG)

0.35 µm ULC

Series with

Embedded

DPRAM

• High Speed Performances:

– 150 ps Typical Gate Delay @3.3V

– Typical 600 MHz Toggle Frequency @3.3V

– Typical 360 MHz Toggle Frequency @2.5V

• High System Frequency Skew Control:

– Clock Tree Synthesis Software

• Low Power Consumption:

– 0.25 µW/Gate/ MHz @3.3V

– 0.18 µW/Gate/ MHz @2.5V

UA1E

• Power on Reset (Internal)

• Standard 2, 4, 6, 8,10, 12 and 18mA I/Os

• CMOS/TTL/PCI LVCMOS, LVTTL, GTL, HSTL, LVDS Interfaces

• ESD (2 kV) and Latch-up Protected I/O

• High Noise & EMC Immunity:

– I/O with Slew Rate Control

– Internal Decoupling

– Signal Filtering between Periphery & Core

• Thick oxide matrices allowing 5V Compliance

• Internal Regulator 5V -> 3.3V

• PLL 0.35µm with Integrated Filter

Description

The UA1E series of ULCs is well suited for conversion of large sized CPLDs and

FPGAs. We can support within one ULC from 18 Kbits to 390 Kbits DPRAM and from

46 Kgates to 780 Kgates. Typically, ULC die size is 50% smaller than the equivalent

FPGA die size. DPRAM blocks are compatible with Xilinx or Altera FPGA blocks.

Devices are implemented in high–performance CMOS technology with 0.35µm

(drawn) channel lengths, and are capable of supporting flip–flop toggle rates of 200

MHz at 3.3V and 180 MHz at 2.5V, and input to output delays as fast as 150ps at 3.3V.

The architecture of the UA1E series allows for efficient conversion of many PLD archi-

tecture and FPGA device types with higher IO count. A compact RAM cell, along with

the large number of available gates allows the implementation of RAM in FPGA archi-

tectures that support this feature, as well as JTAG boundary–scan and scan–path

testing.

Conversion to the UA1E series of ULC can provide a significant reduction in operating

power when compared to the original PLD or FPGA. This is especially true when com-

pared to many PLD and CPLD architecture devices, which typically consume 100mA

or more even when not being clocked. The UA1E series has a very low standby con-

sumption of 0.3nA/gate typically commercial temperature, which would yield a

standby current of 42µA on a 144,000 gates design. Operating consumption is a strict

Rev. 4319B–ULC–12/03

12 3 4 5 6 7...11

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