USB5807C
2.0
2.1
INTRODUCTION
General Description
The Microchip USB5807C hub is a low-power, OEM configurable, USB 3.1 Gen 1 hub controller with 7 downstream
ports and advanced features for embedded USB applications. The USB5807C is fully compliant with the Universal Serial
Bus Revision 3.1 Specification and USB 2.0 Link Power Management Addendum. The USB5807C supports 5 Gbps
SuperSpeed (SS), 480 Mbps Hi-Speed (HS), 12 Mbps Full-Speed (FS), and 1.5 Mbps Low-Speed (LS) USB down-
stream devices on all enabled downstream ports.
The USB5807C supports the legacy USB speeds (HS/FS/LS) through a dedicated USB 2.0 hub controller that is the
culmination of five generations of Microchip hub controller design and experience with proven reliability, interoperability,
and device compatibility. The SuperSpeed hub controller operates in parallel with the USB 2.0 hub controller, decoupling
the 5 Gbps SS data transfers from bottlenecks due to the slower USB 2.0 traffic.
The USB5807C enables OEMs to configure their system using “Configuration Straps.” These straps simplify the config-
uration process, assigning default values to USB 3.1 Gen 1 ports and GPIOs. OEMs can disable ports, enable battery
charging, and define GPIO functions as default assignments on power-up, removing the need for OTP or external SPI
ROM.
The USB5807C supports downstream battery charging via the integrated battery charger detection circuitry, which sup-
ports the USB-IF Battery Charging (BC1.2) detection method and most Apple devices. The USB5807C provides the
battery charging handshake and supports the following USB-IF BC1.2 charging profiles:
• DCP: Dedicated Charging Port (Power brick with no data)
• CDP: Charging Downstream Port (1.5A with data)
• SDP: Standard Downstream Port (0.5A with data)
• Custom profiles loaded via SMBus or OTP
Additionally, the USB5807C includes many powerful and unique features such as:
FlexConnect, which provides flexible connectivity options. One of the USB5807C’s downstream ports can be reconfig-
ured to become the upstream port, allowing master capable devices to control other devices on the hub.
PortSwap, which adds per-port programmability to USB differential-pair pin locations. PortSwap allows direct alignment
of USB signals (D+/D-) to connectors to avoid uneven trace length or crossing of the USB differential signals on the
PCB.
PHYBoost, which provides programmable levels of Hi-Speed USB signal drive strength
in the downstream port transceivers. PHYBoost attempts to restore USB signal integrity
in a compromised system environment. The graphic on the right shows an example of
Hi-Speed USB eye diagrams before and after PHYBoost signal integrity restoration. in
a compromised system environment.
VariSense, which controls the USB receiver sensitivity enabling programmable levels of USB signal receive sensitivity.
This capability allows operation in a sub-optimal system environment, such as when a captive USB cable is used.
Port Split, which allows for the USB3.1 Gen1 and USB2.0 portions of downstream ports 5 and 6 to operate inde-
pendently and enumerate two separate devices in parallel in special applications.
The USB5807C can be configured for operation through internal default settings. Custom OEM configurations are sup-
ported through external SPI ROM or OTP ROM. All port control signal pins are under firmware control in order to allow
for maximum operational flexibility, and are available as GPIOs for customer specific use.
The USB5807C is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature ranges. An inter-
nal block diagram of the USB5807C is shown in Figure 2-1.
DS00003182A-page 6
2019 Microchip Technology Inc.
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