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UPSD3314D-40T6 PDF预览

UPSD3314D-40T6

更新时间： 2024-02-18 22:35:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 可编程逻辑
页数 文件大小 规格书
231页 3711K
描述
Fast 8032 MCU with Programmable Logic

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UPSD3314D-40T6 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
针数：52Reach Compliance Code：compliant
风险等级：5.84位大小：8
CPU系列：8051JESD-30 代码：S-PQFP-G52
JESD-609代码：e3湿度敏感等级：1
端子数量：52最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装等效代码：QFP52,.47SQ
封装形状：SQUARE封装形式：FLATPACK
峰值回流温度（摄氏度）：225电源：5 V
认证状态：Not QualifiedRAM（字节）：2048
ROM（单词）：262144ROM可编程性：FLASH
速度：40 MHz子类别：Microcontrollers
标称供电电压：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.635 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIEDBase Number Matches：1

UPSD3314D-40T6 数据手册

 浏览型号UPSD3314D-40T6的Datasheet PDF文件第4页浏览型号UPSD3314D-40T6的Datasheet PDF文件第5页浏览型号UPSD3314D-40T6的Datasheet PDF文件第6页浏览型号UPSD3314D-40T6的Datasheet PDF文件第8页浏览型号UPSD3314D-40T6的Datasheet PDF文件第9页浏览型号UPSD3314D-40T6的Datasheet PDF文件第10页 
uPSD33xx  
SUMMARY DESCRIPTION  
The Turbo uPSD33xx Series combines a powerful  
8051-based microcontroller with a flexible memory  
structure, programmable logic, and a rich periph-  
eral mix to form an ideal embedded controller. At  
its core is a fast 4-cycle 8032 MCU with a 6-byte  
instruction prefetch queue (PFQ) and a 4-entry ful-  
ly associative branching cache (BC) to maximize  
MCU performance, enabling loops of code in  
smaller localities to execute extremely fast.  
Code development is easily managed without a  
hardware In-Circuit Emulator by using the serial  
JTAG debug interface. JTAG is also used for In-  
System Programming (ISP) in as little as 10 sec-  
onds, perfect for manufacturing and lab develop-  
ment. The 8032 core is coupled to Programmable  
System Device (PSD) architecture to optimize the  
8032 memory structure, offering two independent  
banks of Flash memory that can be placed at vir-  
tually any address within 8032 program or data ad-  
dress space, and easily paged beyond 64K bytes  
using on-chip programmable decode logic. Dual  
Flash memory banks provide a robust solution for  
remote product updates in the field through In-Ap-  
plication Programming (IAP). Dual Flash banks  
also support EEPROM emulation, eliminating the  
need for external EEPROM chips. General pur-  
pose programmable logic (PLD) is included to  
build an endless variety of glue-logic, saving exter-  
nal logic devices. The PLD is configured using the  
software development tool, PSDsoft Express,  
available from the web at www.st.com/psm, at no  
charge. The uPSD33xx also includes supervisor  
functions such as a programmable watchdog timer  
and low-voltage reset.  
Figure 2. Block Diagram  
uPSD33xx  
(3) 16-bit  
Timer/  
Counters  
1st Flash Memory:  
64K, 128K,  
or 256K Bytes  
Turbo  
8032  
Core  
PFQ  
&
BC  
(2)  
External  
Interrupts  
Programmable  
Decode and  
Page Logic  
2nd Flash Memory:  
I2C  
16K or 32K Bytes  
P3.0:7  
SRAM:  
2K, 8K, or 32K Bytes  
UART0  
(8) GPIO, Port A  
PA0:7  
(80-pin only)  
(8) GPIO, Port 3  
(8) GPIO, Port 1  
(8) 10-bit ADC  
General  
PB0:7  
PD1:2  
(8) GPIO, Port B  
(2) GPIO, Port D  
(4) GPIO, Port C  
Purpose  
Programmable  
Logic,  
P1.0:7  
16 Macrocells  
PC0:7  
Optional IrDA  
Encoder/Decoder  
UART1  
JTAG ICE and ISP  
MCU  
Bus  
8032 Address/Data/Control Bus  
(80-pin device only)  
SPI  
16-bit PCA  
Supervisor:  
(6) PWM, CAPCOM, TIMER  
Watchdog and Low-Voltage Reset  
Dedicated  
Pins  
VCC, VDD, GND, Reset, Crystal In  
(8) GPIO, Port 4  
P4.0:7  
AI08875  
7/231  
1...45678910...231

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