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UPD780984CW-XXX-A PDF预览

UPD780984CW-XXX-A

更新时间: 2024-01-16 18:30:06
品牌 Logo 应用领域
日电电子 - NEC 时钟微控制器光电二极管外围集成电路
页数 文件大小 规格书
429页 2392K
描述
8-BIT, MROM, 12MHz, MICROCONTROLLER, PDIP64, 0.750 INCH, LEAD FREE, PLASTIC, SDIP-64

UPD780984CW-XXX-A 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:DIP
包装说明:SDIP,针数:64
Reach Compliance Code:compliantHTS代码:8542.31.00.01
风险等级:5.78具有ADC:YES
地址总线宽度:8位大小:8
最大时钟频率:12 MHzDAC 通道:NO
DMA 通道:NO外部数据总线宽度:8
JESD-30 代码:R-PDIP-T64JESD-609代码:e1
长度:58 mmI/O 线路数量:47
端子数量:64最高工作温度:85 °C
最低工作温度:-40 °CPWM 通道:YES
封装主体材料:PLASTIC/EPOXY封装代码:SDIP
封装形状:RECTANGULAR封装形式:IN-LINE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
ROM可编程性:MROM座面最大高度:5.08 mm
速度:12 MHz最大供电电压:5.5 V
最小供电电压:4 V标称供电电压:4.5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN SILVER COPPER
端子形式:THROUGH-HOLE端子节距:1.778 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:19.05 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER
Base Number Matches:1

UPD780984CW-XXX-A 数据手册

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Major Revisions in This Edition (1/2)  
Page  
U13029JJ6V0UD00 U13029JJ7V0UD00  
Description  
Throughout  
• Addition of package  
64-pin plastic LQFP (14 x 14)  
µPD780982GC-×××-8BS, 780983GC-×××-8BS, 780984GC-×××-8BS  
µPD780986GC-×××-8BS, 780988GC-×××-8BS, 78F0988AGC-8BS  
µPD780982GC(A)-×××-8BS, 780983GC(A)-×××-8BS, 780984GC(A)-×××-8BS  
µPD780986GC(A)-×××-8BS, 780988GC(A)-×××-8BS  
• Change of power supply voltage range as shown below.  
VDD = 4.0 to 5.5 V VDD = 3.0 to 5.5 V (expanded-specification products), VDD = 4.0 to 5.5 V  
(conventional products)  
• Change of system clock oscillation frequency (fX) as shown below.  
fX = 8.38 MHz fX = 12 MHz (expanded-specification products only), fX =8.38 MHz  
• Change of minimum instruction execution time  
p.26  
Addition of 1.1 Expanded-Specification Products and Conventional Products  
1.6 Pin Configuration (Top View)  
p.30  
p.31  
• Addition of Cautions 2 and 3 to 64-pin plastic SDIP (19.05 mm (750))  
• Addition of Cautions 2 and 3 to 64-pin plastic QFP (14 x 14), 64-pin plastic LQFP (14 x 14)  
p.56  
3.1.2 Internal data memory space  
Addition of description on (1) Internal high-speed RAM and (2) Internal expansion RAM  
p.99  
Modification of Table 5-2 Relationship Between CPU Clock and Minimum Instruction  
Execution Time  
p.105  
p.117  
p.118  
p.123  
p.123  
p.146  
p.147  
p.147  
p.164  
p.173  
p.174  
p.175  
p.177  
p.178  
p.179  
p.204  
Modification of Figure 5-5 Switching Between System Clock and CPU Clock  
Modification of Figure 6-9 Format of Prescaler Mode Register 00  
Modification of Figure 6-10 Format of Prescaler Mode Register 01  
Addition of Figure 6-16 Configuration Diagram of PPG Output  
Addition of Figure 6-17 PPG Output Operation Timing  
Modification of Figure 7-7 Format of Timer Clock Select Register 50  
Modification of Figure 7-8 Format of Timer Clock Select Register 51  
Modification of Figure 7-9 Format of Timer Clock Select Register 52  
Modification of Figure 8-2 Format of Inverter Timer Control Register 7  
Modification of Table 9-1 Loop Detection Time of Watchdog Timer  
Modification of Table 9-2 Interval Time  
Modification of Figure 9-2 Format of Watchdog Timer Clock Select Register  
Modification of Figure 9-4 Format of Oscillation Stabilization Time Select Register  
Modification of Table 9-4 Loop Detection Time of Watchdog Timer  
Modification of Table 9-5 Interval Time of Interval Timer  
11.2 Configuration of A/D Converter  
Addition of register figure to (2) A/D conversion result register 0 (ADCR0)  
p.206  
p.214  
Modification of Figure 11-2 Format of A/D Converter Mode Register 0  
11.5 Notes on A/D Converter  
Addition of (6) Input impedance of ANI0 to ANI7 pins  
p.232  
p.233  
Modification of Figure 12-9 Format of Baud Rate Generator Control Register 0  
Modification of Figure 12-10 Format of Baud Rate Generator Control Register 1  
User’s Manual U13029EJ7V1UD  
7

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