APPENDIX D REVISION HISTORY
D.1 Modifications from Document Number U15862EJ4V1UD00
Page
Description
Throughout
• Extraction of only descriptions concerning V850ES/KG1
• Addition of 100-pin plastic QFP (14 × 20)
• Addition of following products
µPD703215, 703215Y, 70F3214H, 70F3214HY, 70F3215H, 70F3215HY
• Addition of pins supporting added products
• Addition of internal ROM, RAM, and flash memory capacities of added products
p. 40
p. 53
p. 63
p. 68
p. 70
p. 76
p. 89
Modification of description in 1.7 Overview of Functions
Modification of I/O circuit type 13-B to 13-AH in 2.4 Pin I/O Circuits
Modification of description in 3.3 (2) Flash memory programming mode
Addition of 3.4.4 (1) (a) Internal ROM (256 KB)
Addition of 3.4.4 (2) (a) Internal RAM (16 KB)
Modification of description in 3.4.6 Peripheral I/O registers
Modification of description in 3.4.8 (1) (a) System wait control register (VSWC) and (b) Access to special
on-chip peripheral I/O register
p. 92
Addition of 3.4.8 (2) Restriction on conflict between sld instruction and interrupt request
Addition of 4.3 (5) Port n function control expansion register (PFCEn)
Modification of description in Figure 4-1 Register Settings and Pin Functions
Modification of description in 4.3.3 (5) Port 3 function control register (PFC3)
Addition of 4.3.3 (6) Port 3 function control expansion register (PFCE3)
Addition of 4.3.3 (8) Specifying alternate-function pins of port 3
p. 96
p. 98
p. 107
p. 108
p. 108
pp. 134 to 159
p. 161
p. 206
p. 503
p. 633
p. 656
p. 698
Modification of Figures 4-3 to 4-28 (partial addition)
Modification of description in Table 4-16 Settings When Port Pins Are Used for Alternate Functions
Addition of CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
Addition of Caution 1 in 18.3 (7) CSIAn buffer RAM (CSIAnBm)
Modification of bit 7 in 22.2 (2) Power save mode register (PSMR)
Addition of CHAPTER 26 FLASH MEMORY (SINGLE POWER)
Addition of CHAPTER 28 ELECTRICAL SPECIFICATIONS (256 KB MASK ROM VERSION, SINGLE-
POWER FLASH MEMORY VERSION) (TARGET)
pp. 761 to 783
Modification of bus timing, basic operation, and timer timing in CHAPTER 29 ELECTRICAL
SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION OF 128 KB OR LESS AND TWO-
POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS)
pp. 805, 806
pp. 826, 827
Modification of basic operation and timer timing in CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A1)
GRADE PRODUCTS)
Modification of basic operation and timer timing in CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A2)
GRADE PRODUCTS)
p. 839
p. 845
Addition of APPENDIX A DEVELOPMENT TOOLS
Addition of APPENDIX B INSTRUCTION SET LIST
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User’s Manual U16890EJ1V0UD