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UPD703215YGF-XXX-JBT PDF预览

UPD703215YGF-XXX-JBT

更新时间: 2024-01-02 13:45:11
品牌 Logo 应用领域
日电电子 - NEC 微控制器
页数 文件大小 规格书
861页 4423K
描述
32-Bit Single-Chip Microcontrollers

UPD703215YGF-XXX-JBT 技术参数

是否Rohs认证: 符合生命周期:Transferred
包装说明:14 X 14 MM, LEAD FREE, PLASTIC, LQFP-100Reach Compliance Code:compliant
风险等级:5.77具有ADC:YES
地址总线宽度:22位大小:32
最大时钟频率:10 MHzDAC 通道:YES
DMA 通道:NO外部数据总线宽度:16
JESD-30 代码:S-PQFP-G100JESD-609代码:e6/e4
长度:14 mmI/O 线路数量:84
端子数量:100最高工作温度:85 °C
最低工作温度:-40 °CPWM 通道:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):260认证状态:Not Qualified
ROM可编程性:MROM座面最大高度:1.6 mm
速度:20 MHz最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN BISMUTH/NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:10
宽度:14 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER, RISC
Base Number Matches:1

UPD703215YGF-XXX-JBT 数据手册

 浏览型号UPD703215YGF-XXX-JBT的Datasheet PDF文件第855页浏览型号UPD703215YGF-XXX-JBT的Datasheet PDF文件第856页浏览型号UPD703215YGF-XXX-JBT的Datasheet PDF文件第857页浏览型号UPD703215YGF-XXX-JBT的Datasheet PDF文件第858页浏览型号UPD703215YGF-XXX-JBT的Datasheet PDF文件第859页浏览型号UPD703215YGF-XXX-JBT的Datasheet PDF文件第860页 
APPENDIX D REVISION HISTORY  
D.1 Modifications from Document Number U15862EJ4V1UD00  
Page  
Description  
Throughout  
Extraction of only descriptions concerning V850ES/KG1  
Addition of 100-pin plastic QFP (14 × 20)  
Addition of following products  
µPD703215, 703215Y, 70F3214H, 70F3214HY, 70F3215H, 70F3215HY  
Addition of pins supporting added products  
Addition of internal ROM, RAM, and flash memory capacities of added products  
p. 40  
p. 53  
p. 63  
p. 68  
p. 70  
p. 76  
p. 89  
Modification of description in 1.7 Overview of Functions  
Modification of I/O circuit type 13-B to 13-AH in 2.4 Pin I/O Circuits  
Modification of description in 3.3 (2) Flash memory programming mode  
Addition of 3.4.4 (1) (a) Internal ROM (256 KB)  
Addition of 3.4.4 (2) (a) Internal RAM (16 KB)  
Modification of description in 3.4.6 Peripheral I/O registers  
Modification of description in 3.4.8 (1) (a) System wait control register (VSWC) and (b) Access to special  
on-chip peripheral I/O register  
p. 92  
Addition of 3.4.8 (2) Restriction on conflict between sld instruction and interrupt request  
Addition of 4.3 (5) Port n function control expansion register (PFCEn)  
Modification of description in Figure 4-1 Register Settings and Pin Functions  
Modification of description in 4.3.3 (5) Port 3 function control register (PFC3)  
Addition of 4.3.3 (6) Port 3 function control expansion register (PFCE3)  
Addition of 4.3.3 (8) Specifying alternate-function pins of port 3  
p. 96  
p. 98  
p. 107  
p. 108  
p. 108  
pp. 134 to 159  
p. 161  
p. 206  
p. 503  
p. 633  
p. 656  
p. 698  
Modification of Figures 4-3 to 4-28 (partial addition)  
Modification of description in Table 4-16 Settings When Port Pins Are Used for Alternate Functions  
Addition of CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)  
Addition of Caution 1 in 18.3 (7) CSIAn buffer RAM (CSIAnBm)  
Modification of bit 7 in 22.2 (2) Power save mode register (PSMR)  
Addition of CHAPTER 26 FLASH MEMORY (SINGLE POWER)  
Addition of CHAPTER 28 ELECTRICAL SPECIFICATIONS (256 KB MASK ROM VERSION, SINGLE-  
POWER FLASH MEMORY VERSION) (TARGET)  
pp. 761 to 783  
Modification of bus timing, basic operation, and timer timing in CHAPTER 29 ELECTRICAL  
SPECIFICATIONS (STANDARD PRODUCTS (MASK ROM VERSION OF 128 KB OR LESS AND TWO-  
POWER FLASH MEMORY VERSION), (A) GRADE PRODUCTS)  
pp. 805, 806  
pp. 826, 827  
Modification of basic operation and timer timing in CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A1)  
GRADE PRODUCTS)  
Modification of basic operation and timer timing in CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A2)  
GRADE PRODUCTS)  
p. 839  
p. 845  
Addition of APPENDIX A DEVELOPMENT TOOLS  
Addition of APPENDIX B INSTRUCTION SET LIST  
861  
User’s Manual U16890EJ1V0UD  

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