Datasheet > UPD4442182GF-A60Y

UPD4442182GF-A60Y

更新时间： 2024-02-23 12:11:15

品牌	Logo	应用领域
瑞萨 - RENESAS		静态存储器
页数	文件大小	规格书
28页	209K
描述
IC,SYNC SRAM,256KX18,CMOS,QFP,100PIN,PLASTIC

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PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

µPD4442162-Y, 4442182-Y, 4442322-Y, 4442362-Y

4M-BIT CMOS SYNCHRONOUS FAST SRAM

PIPELINED OPERATION

SINGLE CYCLE DESELECT

Description

The µPD4442162-Y is a 262,144-word by 16-bit, the µPD4442182-Y is a 262,144-word by 18-bit, µPD4442322-Y is

a 131,072-word by 32-bit and the µPD4442362-Y is a 131,072-word by 36-bit synchronous static RAM fabricated with

advanced CMOS technology using Full-CMOS six-transistor memory cell.

The µPD4442162-Y, µPD4442182-Y, µPD4442322-Y and µPD4442362-Y integrates unique synchronous peripheral

circuitry, 2-bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive

edge of the single clock input (CLK).

The µPD4442162-Y, µPD4442182-Y, µPD4442322-Y and µPD4442362-Y are suitable for applications which require

synchronous operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer

memory.

ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State

(“Sleep”). In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes

normal operation.

The µPD4442162-Y, µPD4442182-Y, µPD4442322-Y and µPD4442362-Y are packaged in 100-pin PLASTIC LQFP

with a 1.4 mm package thickness for high density and low capacitive loading.

Features

• 3.3 V (A version) or 2.5 V (C version) Core Supply

• Synchronous operation

• Extended operating temperature (T^A= –40 to +85 °C)

• Internally self-timed write control

• Burst read / write : Interleaved burst and linear burst sequence

• Fully registered inputs and outputs for pipelined operation

• Single-Cycle deselect timing

• All registers triggered off positive clock edge

• 3.3 V or 2.5 V LVTTL Compatible : All inputs and outputs

• Fast clock access time : 2.5 ns (250 MHz), 2.8 ns (225 MHz), 3.0 ns (200 MHz), 3.5 ns (167 MHz)

• Asynchronous output enable : /G

• Burst sequence selectable : MODE

• Sleep mode : ZZ (ZZ = Open or Low : Normal operation)

• Separate byte write enable : /BW1 - /BW4 (µPD4442322-Y, µPD4442362-Y), /BW1 - /BW2 (µPD4442162-Y,

µPD4442182-Y), /BWE

Global write enable : /GW

• Three chip enables for easy depth expansion

• Common I/O using three state outputs

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No. M15503EJ2V0DS00 (2nd edition)

Date Published May 2001 NS CP(K)

Printed in Japan

The mark ! shows major revised points.

2001

12 3 4 5 6 7...28

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与UPD4442182GF-A60Y相关器件

型号	品牌	描述	获取价格	数据表
UPD4442182GF-C50Y	RENESAS	Cache SRAM, 256KX18, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-100	获取价格
UPD4442182GF-C60Y	RENESAS	Cache SRAM, 256KX18, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-100	获取价格
UPD4442321GF-A65	RENESAS	IC,SYNC SRAM,128KX32,CMOS,QFP,100PIN,PLASTIC	获取价格
UPD4442321GF-A75	RENESAS	Cache SRAM, 128KX32, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-100	获取价格
UPD4442321GF-A85	RENESAS	IC,SYNC SRAM,128KX32,CMOS,QFP,100PIN,PLASTIC	获取价格
UPD4442321GF-C75	RENESAS	Cache SRAM, 128KX32, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-100	获取价格

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