Datasheet > UPD4442321GF-A75

UPD4442321GF-A75

更新时间： 2024-10-15 10:06:51

品牌	Logo	应用领域
瑞萨 - RENESAS		静态存储器
页数	文件大小	规格书
24页	196K
描述
Cache SRAM, 128KX32, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-100

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UPD4442321GF-A75 数据手册

PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

PD4442161, 4442181, 4442321, 4442361

4M-BIT CMOS SYNCHRONOUS FAST SRAM

FLOW THROUGH OPERATION

Description

The µPD4442161 is a 262,144-word by 16-bit, the µPD4442181 is a 262,144-word by 18-bit, the µPD4442321 is a

131,072-word by 32-bit and the µPD4442361 is a 131,072-word by 36-bit synchronous static RAM fabricated with

advanced CMOS technology using Full-CMOS six-transistor memory cell.

The µPD4442161, µPD4442181, µPD4442321 and µPD4442361 integrate unique synchronous peripheral circuitry,

2-bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the

single clock input (CLK).

The µPD4442161, µPD4442181, µPD4442321 and µPD4442361 are suitable for applications which require

synchronous operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer

memory.

ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”).

In the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal

operation.

The µPD4442161, µPD4442181, µPD4442321 and µPD4442361 are packaged in 100-pin PLASTIC LQFP with a

1.4 mm package thickness for high density and low capacitive loading.

Features

• 3.3 V (A version) or 2.5 V (C version) Core Supply

• Synchronous operation

• Internally self-timed write control

• Burst read / write : Interleaved burst and linear burst sequence

• Fully registered inputs for flow through operation

• All registers triggered off positive clock edge

• 3.3 V or 2.5 V LVTTL Compatible : All inputs and outputs

• Fast clock access time : 6.5 ns (133 MHz), 7.5 ns (117 MHz), 8.5 ns (100 MHz)

• Asynchronous output enable : /G

• Burst sequence selectable : MODE

• Sleep mode : ZZ (ZZ = Open or Low : Normal operation)

• Separate byte write enable : /BW1 - /BW4 (µPD4442321, µPD4442361), /BW1 - /BW2 (µPD4442161,

µPD4442181), /BWE

Global write enable : /GW

• Three chip enables for easy depth expansion

• Common I/O using three state outputs

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

The mark ★ shows major revised points.

Document No. M14519EJ2V0DS00 (2nd edition)

Date Published May 2001 NS CP(K)

Printed in Japan

2000

12 3 4 5 6 7...24

中文翻译

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与UPD4442321GF-A75相关器件

型号	品牌	获取价格	描述	数据表
UPD4442321GF-A85	RENESAS	获取价格	IC,SYNC SRAM,128KX32,CMOS,QFP,100PIN,PLASTIC
UPD4442321GF-C75	RENESAS	获取价格	Cache SRAM, 128KX32, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-100
UPD4442321GF-C85	RENESAS	获取价格	IC,SYNC SRAM,128KX32,CMOS,QFP,100PIN,PLASTIC
UPD4442322GF-A44CY	RENESAS	获取价格	IC,SYNC SRAM,128KX32,CMOS,QFP,100PIN,PLASTIC
UPD4442322GF-A44Y	RENESAS	获取价格	IC,SYNC SRAM,128KX32,CMOS,QFP,100PIN,PLASTIC
UPD4442322GF-A50Y	RENESAS	获取价格	Cache SRAM, 128KX32, 3ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-100
UPD4442322GF-A60CY	RENESAS	获取价格	Cache SRAM, 128KX32, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-100
UPD4442322GF-A60Y	RENESAS	获取价格	Cache SRAM, 128KX32, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, LQFP-100
UPD4442361GF-A85	RENESAS	获取价格	IC,SYNC SRAM,128KX36,CMOS,QFP,100PIN,PLASTIC
UPD4442361GF-C75	RENESAS	获取价格	IC,SYNC SRAM,128KX36,CMOS,QFP,100PIN,PLASTIC

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