Datasheet > UPB1008K

UPB1008K

更新时间： 2024-02-21 10:06:22

品牌	Logo	应用领域
CEL		射频全球定位系统
页数	文件大小	规格书
10页	403K
描述
LOW POWER GPS RF RECEIVER

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技术参数
数据手册

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UPB1008K 技术参数

生命周期：	Obsolete	零件包装代码：	QFN
包装说明：	VQCCN,	针数：	36
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.74	模拟集成电路 - 其他类型：	PLL FREQUENCY SYNTHESIZER
JESD-30 代码：	S-PQCC-N36	长度：	6 mm
功能数量：	1	端子数量：	36
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	VQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, VERY THIN PROFILE
认证状态：	Not Qualified	座面最大高度：	1 mm
最大供电电压 (Vsup)：	3.3 V	最小供电电压 (Vsup)：	2.7 V
标称供电电压 (Vsup)：	3 V	表面贴装：	YES
技术：	BIPOLAR	温度等级：	INDUSTRIAL
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	6 mm
Base Number Matches：	1

UPB1008K 数据手册

UPB1008K

PIN FUNCTIONS

Pin No.

Symbol

Function and Application

Internal Equivalent Circuit

GNDbb

Qmag

Qsign

Isign

Imag

VCCbb

Ground pin of CMOS output driver.

Digitized Q signal. Magnitude bit of 2-bit ADC output.

Digitized Q signal. Sign bit of 2-bit ADC output

Digitized I signal. Sign bit of 2-bit ADC output.

Digitized I signal. Magnitude bit of 2-bit ADC output.

Supply voltage pin of CMOS output driver.

r=21.5

r=5k

ESD

19, (20,21,22)

ESD

DCoffsetIb

DCoffsetI

DC offset compensation pin for I-bar arm.

A low pass capacitor shunt to Pin 25 is required.

DC offset compensation pin for I arm.

A low pass capacitor shunt to Pin 24 is required.

Differential output pins of quadrature

demodulator I output. Adding a lowpass shunt

capacitor between these pins will define the

IF bandwidth.

See pin 16 & 17 schematic

See pin 14 & 15 schematic

2IFout-Ib

2IFout-I

VCC if

VAGC

Supply voltage pin of analog portion of the chip.

Gain control voltage pin of IF amplifier. This voltage

performs reverse control,(i.e., VAGC up → gain down).

If this pin is left open, then it is default at

maximum gain.

r=300

ESD

To AGC Amp

Typical AGC

Gain Response

r=3k

ESD

-15

0.5

1.5

VAGC (V)

IF-in1

IF-in2

GNDanalog

Differential input pins of 1st IF AGC amplifier

Ground pin of analog portion of the chip.

r=4k

r=2k

r=4k

Regulator

ESD

r=4k

ESD

r=4k

r=1.42k

ESD

Mixout2

Mixout1

Differential output pins of RF mixer. This is an emitter

follower output buffer, provide a 50Ω output load.

ESD

c=1.67p

Regulator

ESD

c=1.67p

ESD

r=111

1...4 5 678 9 10

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与UPB1008K相关器件

型号	品牌	描述	获取价格	数据表
UPB1008K-A	CEL	LOW POWER GPS RF RECEIVER	获取价格
UPB1008K-E1	NEC	PLL Frequency Synthesizer, BIPolar, PQCC36, PLASTIC, QFN-36	获取价格
UPB1008K-E1	RENESAS	PLL FREQUENCY SYNTHESIZER, PQCC36, PLASTIC, QFN-36	获取价格
UPB1008K-E1-A	NEC	暂无描述	获取价格
UPB1009K	NEC	NECs LOW POWER GPS RF RECEIVER BIPOLAR ANALOG + INTEGRATED CIRCUIT	获取价格
UPB1009K	CEL	LOW POWER GPS RF RECEIVER BIPOLAR ANALOG + INTEGRATED CIRCUIT	获取价格