uP8206
Test Circuit
(1) Test Condition 1, Test Circuit 1
(4) Test Condition 4, Test Circuit 2
Set V1, V2, V3, and V4 to 3.5V. Overcharge detection In the uP8206A/P Series, set V1, V2, V3, and V4 to 3.5V
voltage 1 (VCU1) is the V1 voltage when CO is H after the and V5 to 14V. The CTL pin response time (tCTL) is the
voltage of V1 has been gradually increased. The overcharge period from when V5 reaches 0 V after V5 is in a moment
hysteresis voltage (VHC1) is the difference between V1 and of time (within 10us) decreased down to 0V to when CO
VCU1 when CO is L after the voltage of V1 has been gradually becomes H.
decreased. Overcharge detection voltage VCUn (n = 2 to 4)
(5) Test Condition 6, Test Circuit 2
and overcharge hysteresis VHCn (n = 2 to 4) can be
Set V1, V2, V3, and V4 to 3.5V and V5 to 0V. The CTL
determined in the same way as when n = 1.
input H voltage (VCTLH) is the maximum voltage of V5 when
CO is L after V5 has been gradually increased. Next, set
(2) Test Condition 2, Test Circuit 1
Set V1, V2, V3, and V4 to 3.5V and in a moment of time V5 to 14V. The CTL input L voltage (VCTLL) is the minimum
(within 10us) increase V1 up to 5.0V. The overcharge voltage of V5 when CO is H after V5 has been gradually
detection delay time (tCU) is the period from whenV1 reached decreased.
5.0V to when CO becomes H. After that, in a moment of
time (within 10us) decrease V1 down to 3.5V. The
overcharge release delay time (tCL) is the period from when
V1 has reached 3.5V to when CO becomes L.
VDD
SENSE
VC1
CO
CTL
VSS
VC3
V
(3) Test Condition 3, Test Circuit 1
V1
V2
V3
V5
V4
Set V1, V2, V3, and V4 to 3.5V and in a moment of time
(within 10us) increase V1 up to 5.0V. This is defined as the
first rise. Within tCU 20 ms after the first rise, in a moment
of time (within 10us) decrease V1 down to 3.5V and then
in a moment of time (within 10us) restore up to 5.0V. This
is defined as the second rise. When the period from when
V1 was fallen to the second rise is short, CO becomes H
after tCU has elapsed since the first rise. If the period from
when V1 falls to the second rise is gradually made longer,
CO becomes H when tCU has elapsed since the second
rise. The overcharge timer reset delay time (tTR) is the period
from V1 fall till the second rise at that time.
VC2
uP8206
Test Circuit 2
(6) Test Condition 5, Test Circuit 3
After setting V1, V2, V3, and V4 to 3.5V and V5 to 0V, in
a moment of time (within 10us) increase V5 up to 8.5V and
decrease V5 again down to 0V. When the period from when
V5 was raised to when it has fallen is short, if an overcharge
detection operation is performed subsequently, the
overcharge detection time is tCU. However, when the period
from when V5 is raised to when it is fallen is gradually
made longer, the overcharge detection time during the
subsequent overcharge detection operation is shorter than
tCU. The transition time to test mode (tTST) is the period
from when V5 was raised to when it has fallen at that time.
VDD
SENSE
VC1
CO
CTL
VSS
VC3
V
V1
V2
V3
V4
VC2
VDD
SENSE
VC1
CO
CTL
VSS
VC3
V5
uP8206
V
Test Circuit 1
V1
V2
V3
V4
VC2
uP8206
Test Circuit 3
6
uP8206-DS-F0001, Apr. 2018
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