uP7706
Functional Description
Definitions
It’s recommended to maintain 50-100uA through the output
divider network for a tight load and line regulation. The
internal voltage reference is VREF = 0.8V with 1.5%
accuracy over full temperature range. This commands the
use of 0.5% or better accuracy resistors to build a precision
power supply.
Some important terminologies for LDO are specified below.
Dropout Voltage
The input/output voltage differential at which the regulator
output no longer maintains regulation against further
reductions in input voltage. Measured when the output drops
2% below its nominal value.Dropout voltage is affected by
junction temperature, load current and minimum input
supply requirements.
5VCC
CNTL
4
C1
0.1uF
EN
POK
VOUT
FB
2
1
6
7
R3
10K
Line Regulation
VOUT
VIN
VIN
3
R2
The change in output voltage for a change in input voltage.
The measurement is made under conditions of low
dissipation or by using pulse techniques such that average
chip temperature is not significantly affected.
C2
C4
12.5K
22uF
option
C3
100uF
R1
10K
8
GND
Load Regulation
The change in output voltage for a change in load current
at constant chip temperature. The measurement is made
under conditions of low dissipation or by using pulse
techniques such that average chip temperature is not
significantly affected.
Figure 1. Typical application of 2.5V to 1.8V conversion
with a 5.0V control supply
Over Current Protection
The uP7706 features a foldback over current protection
function as shown in Figure 2. The current limit threshold
level is proportional to VOUT/VNOM and is typically 4A when
Maximum Power Dissipation
The maximum total device dissipation for which the
regulator will operate within specifications.
V
OUT = VNOM, where VNOM is the target output voltage. If the
output continuously demands more current than the
maximum current, output voltage will eventually drops below
its nominal value. This, in turns, will lower its OCP threshold
level. This will limit power dissipation in the device when
over current limit happens. The power dissipation is near
zero when the output is short circuited to ground.
Initialization
The uP7706 automatically initiates upon the receipt of
supply voltage and power voltage.Apower on reset circuit
continuously monitors VIN and CNTL pins voltages with
rising threshold levels of 1.0V and 2.7V respectively.
Chip Enable and Soft Start
The uP7706 features an enable pin for enable/disable
control of the chip. Pulling VEN lower than 0.8V disables
the chip and reduces its quiescent current down to 1uA.
When disabled, an internal MOSFET of 90Ω RDS(ON) turns
on to pull output voltage to ground. Pulling VEN higher than
2.0V enables the output voltage, providing POR is
recognized. The uP7706 features soft start function that
limits inrush current for charging the output capacitors. The
soft start time is typically 2.5ms.
VOUT
3V
2A
1V
Output Voltage Programming
IOUT
0A
1A
2A
3A
4A
Figure 1 shows a typical application of 2.5V to 1.8V
conversion with a 5.0V control supply. The output voltage
is sensed through a voltage divider and regulated to internal
reference voltage VREF. The output voltage is programmed
as:
Figure 2. Current Limit Behavior
VOUT = VREF x (R1+R2) / R1 = 0.8V x (22.5k/10k) = 1.8V
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP7706-DS-F0000
3
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