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UCQ5810AF

更新时间： 2024-01-14 09:23:49
品牌 Logo 应用领域
急速微 - ALLEGRO 驱动器输入元件
页数 文件大小 规格书
8页 159K
描述
BiMOS II 10-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS

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UCQ5810AF 数据手册

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5810-F  
10-BIT SERIAL-INPUT,  
LATCHED SOURCE DRIVERS  
WITH ACTIVE-DMOS PULL-DOWNS  
Serial Data present at the input is transferred  
to the shift register on the logic “0” to logic “1”  
transition of the CLOCK input pulse. On  
succeeding CLOCK pulses, the registers shift data  
information towards the SERIAL DATA OUT-  
PUT. The SERIAL DATA must appear at the  
input prior to the rising edge of the CLOCK input  
waveform.  
CLOCK  
A
D
B
DATA IN  
STROBE  
BLANKING  
OUTN  
E
F
C
Information present at any register is trans-  
ferred to the respective latch when the STROBE  
is high (serial-to-parallel conversion). The  
latches will continue to accept new data as long as  
the STROBE is held high. Applications where  
the latches are bypassed (STROBE tied high) will  
require that the BLANKING input be high during  
serial data entry.  
G
Dwg. No. A-12,649A  
TIMING REQUIREMENTS  
(TA = +25°C,VDD = 5 V, Logic Levels are VDD and Ground)  
A. Minimum Data Active Time Before Clock Pulse  
(Data Set-Up Time).......................................................................... 75 ns  
When the BLANKING input is high, the  
output source drivers are disabled (OFF); the  
DMOS sink drivers are ON. The information  
stored in the latches is not affected by the  
BLANKING input. With the BLANKING input  
low, the outputs are controlled by the state of  
their respective latches.  
B. Minimum Data Active Time After Clock Pulse  
(Data Hold Time) ............................................................................. 75 ns  
C. Minimum Data Pulse Width ................................................................ 150 ns  
D. Minimum Clock Pulse Width............................................................... 150 ns  
E. Minimum Time Between Clock Activation and Strobe ....................... 300 ns  
F. Minimum Strobe Pulse Width ............................................................. 100 ns  
G. Typical Time Between Strobe Activation and  
Output Transistion ......................................................................... 500 ns  
Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable  
with increased supply voltage; operation at high temperatures will reduce the  
specified maximum clock frequency.  
TRUTH TABLE  
Serial  
Data Clock  
Input Input I  
Shift Register Contents  
Serial  
Data Strobe  
Output Input  
Latch Contents  
Output Contents  
... I  
I
I
...  
I
I
I
I
I
...  
I
I
Blanklng  
I
I
I
I
N-1 N  
1
2
3
N-1  
N
1
2
3
N-1  
N
1
2
3
H
L
H
L
R
R
R
X
R
R
R
X
...  
...  
...  
...  
...  
R
R
R
X
R
R
R
X
R
R
R
X
1
1
2
2
2
3
N-2  
N-2  
N-1  
N-1  
N-1  
N
N-1  
N-1  
N
X
R
X
1
L
R
R
R
...  
...  
...  
R
R
1
2
3
N-1  
N
P
P
P
P
P
P
H
P
X
P
X
P
X
P
X
P
L
P
L
P
L
P
L
... P  
... L  
P
L
1
2
3
N-1  
N
N
1
2
3
N-1  
N
1
2
3
N-1  
N
X
H
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State  
115 Northeast Cutoff, Box 15036  
Worcester, Massachusetts 01615-0036 (508) 853-5000  
12345678

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