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UC386DWTR

更新时间： 2024-02-03 21:55:44
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
9页 474K
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UC386DWTR

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UC386DWTR 技术参数

生命周期：ObsoleteReach Compliance Code：unknown
风险等级：5.84Is Samacsys：N
Base Number Matches：1

UC386DWTR 数据手册

 浏览型号UC386DWTR的Datasheet PDF文件第3页浏览型号UC386DWTR的Datasheet PDF文件第4页浏览型号UC386DWTR的Datasheet PDF文件第5页浏览型号UC386DWTR的Datasheet PDF文件第6页浏览型号UC386DWTR的Datasheet PDF文件第8页浏览型号UC386DWTR的Datasheet PDF文件第9页 
UC1861-1868  
UC2861-2868  
UC3861-3868  
APPLICATION INFORMATION  
Minimum oscillator frequency is set by Rmin and Cvco. The Error Amplifier directly controls the oscillator fre-  
The minimum frequency is approximately given by the quency. E/A output low corresponds to minimum fre-  
equation:  
quency and output high corresponds to maximum  
frequency. At the end of each oscillator cycle, the RC pin  
is discharged to one diode drop above ground. At the be-  
ginning of the oscillator cycle, V(RC) is less than Vth1  
and so the output of the zero detect comparator is ig-  
nored. After V(RC) exceeds Vth1, the one shot pulse will  
be terminated as soon as the zero pin falls below 0.5V or  
V(RC) exceeds Vth2. The minimum one shot pulse width  
is approximately given by the equation:  
4.3  
FMIN  
RMIN • CVCO  
Maximum oscillator frequency is set by Rmin, Range &  
Cvco. The maximum frequency is approximately given by  
the equation:  
3.3  
FMAX  
(RMIN / / Range )• CVCO  
Tpw(min) 0.3  
The maximum pulse width is approximately given by:  
Tpw(max) 1.2 C.  
R
C.  
R
STEERING LOGIC  
UDG-92014  
UDG-92013  
The steering logic is configured on the UC1861,63 to result in  
dual non-overlapping square waves at outputs A & B. This is  
suited to drive dual switch ZVS systems.  
The steering logic is configured on the UC1862,64 to result in  
inverted pulse trains occurring identically at both output pins.  
This is suited to drive single switch ZVS systems. Both outputs  
are available to drive the same MOSFET gate. It is advisable  
to join the pins with 0.5 ohm resistors.  
UDG-92015  
The steering logic is configured on the UC1865,67 to result in  
alternating pulse trains at outputs A & B. This is suited to drive  
dual switch ZCS systems.  
UDG-92016  
The steering logic is configured on the UC1866,68 to result in  
non-inverted pulse trains occurring identically at both output  
pins. This is suited to drive single switch ZCS systems. Both  
outputs are available to drive the same MOSFET gate. It is ad-  
visable to join the pins with 0.5 ohm resistors.  
7
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