Preliminary
U633H04
NONVOLATILE MEMORY OPERATIONS
MODE SELECTION
A8 - A0
(hex)
E
W
HSB
Mode
I/O
Power
Notes
H
L
X
H
L
H
H
H
L
X
X
X
X
Not Selected
Read SRAM
Write SRAM
STORE/Inhibit
Output High Z
Output Data
Input Data
Standby
Active
l
L
Active
X
X
Output High Z
I
CC2/Standby
m
k: reserved for future development
l: I/O state assumes that G ≤ VIL. Activation of nonvolatile cycles does not depend on the state of G.
m: HSB initiated STORE operation actually occurs only if a WRITE has been done since last STORE operation. After the STORE (if any)
completes, the part will go into standby mode inhibiting all operation until HSB rises.
Symbol
PowerStore Power Up RECALL/
No.
Conditions
Min. Max. Unit
Hardware Controlled STORE
Alt.
IEC
24 Power Up RECALL Durationn, e
25 STORE Cycle Duration
26 HSB Low to Inhibit One
27 HSB High to Inhibit Offe
28 External STORE Pulse Widthe
HSB Output Low Currente, o
HSB Output High Currente, o
Low Voltage Trigger Level
tRESTORE
tHLQX
650
10
µs
ms
µs
ns
ns
mA
µA
V
>
td(H)S
tdis(H)S
ten(H)S
tw(H)S
VCC 4.5 V
tHLQZ
1
tHHQX
700
tHLHX
250
3
IHSBOL
IHSBOH
VSWITCH
HSB = VOL
HSB = VIL
5
60
4.0
4.5
n: An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE
SWITCH once it has been exceeded for the RECALL to function properly.
. VCC must not drop below
V
o: HSB is an I/O that has a week internal pullup; it is basically an open drain output. It is meant to allow up to 32 U633H04 to be ganged
together for simultaneous storing. Do not use HSB to pullup any external circuitry other than other U633H04 HSB pins.
7
December 12, 1997