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U632H64DK35 PDF预览

U632H64DK35

更新时间: 2024-01-05 20:05:01
品牌 Logo 应用领域
其他 - ETC 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
14页 157K
描述
NVRAM (EEPROM Based)

U632H64DK35 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Transferred零件包装代码:DIP
包装说明:DIP, DIP28,.3针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.13
最长访问时间:35 nsJESD-30 代码:R-PDIP-T28
JESD-609代码:e0长度:34.7 mm
内存密度:65536 bit内存集成电路类型:NON-VOLATILE SRAM
内存宽度:8湿度敏感等级:3
功能数量:1端口数量:1
端子数量:28字数:8192 words
字数代码:8000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:8KX8输出特性:3-STATE
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP28,.3
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
座面最大高度:5.1 mm最大待机电流:0.003 A
子类别:SRAMs最大压摆率:0.085 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

U632H64DK35 数据手册

 浏览型号U632H64DK35的Datasheet PDF文件第2页浏览型号U632H64DK35的Datasheet PDF文件第3页浏览型号U632H64DK35的Datasheet PDF文件第4页浏览型号U632H64DK35的Datasheet PDF文件第5页浏览型号U632H64DK35的Datasheet PDF文件第6页浏览型号U632H64DK35的Datasheet PDF文件第7页 
U632H64  
PowerStore 8K x 8 nvSRAM  
Features  
Description  
F High-performance CMOS non-  
volatile static RAM 8192 x 8 bits  
F 25, 35 and 45 ns Access Times  
F 12, 20 and 25 ns Output Enable  
Access Times  
The U632H64 has two separate ware sequence or via a single pin  
modes of operation: SRAM mode (HSB).  
and nonvolatile mode. In SRAM Once a STORE cycle is initiated,  
mode, the memory operates as an further input or output are disabled  
ordinary static RAM. In nonvolatile until the cycle is completed.  
F ICC = 15 mA at 200 ns Cycle Time operation, data is transferred in Because a sequence of addresses  
F Automatic STORE to EEPROM  
on Power Down using external  
capacitor  
parallel from SRAM to EEPROM or is used for STORE initiation, it is  
from EEPROM to SRAM. In this important that no other read or  
mode SRAM functions are disab- write accesses intervene in the  
F Hardware or Software initiated  
STORE  
led.  
sequence or the sequence will be  
The U632H64 is a fast static RAM aborted.  
(STORE Cycle Time < 10 ms)  
F Automatic STORE Timing  
F 105 STORE cycles to EEPROM  
F 10 years data retention in  
EEPROM  
F Automatic RECALL on Power Up  
F Software RECALL Initiation  
(RECALL Cycle Time < 20 µs)  
F Unlimited RECALL cycles from  
EEPROM  
(25, 35, 45 ns), with a nonvolatile RECALL cycles may also be initia-  
electrically  
erasable  
PROM ted by a software sequence.  
(EEPROM) element incorporated Internally, RECALL is a two step  
in each static memory cell. The procedure. First, the SRAM data is  
SRAM can be read and written an cleared and second, the nonvola-  
unlimited number of times, while tile information is transferred into  
independent nonvolatile data resi- the SRAM cells.  
des in EEPROM. Data transfers The RECALL operation in no way  
from the SRAM to the EEPROM alters the data in the EEPROM  
(the STORE operation) take place cells. The nonvolatile data can be  
automatically upon power down recalled an unlimited number of  
using charge stored in an external times.  
F Single 5 V ± 10 % Operation  
F Operating temperature ranges:  
0 to 70 °C  
100 µF capacitor. Transfers from  
-40 to 85 °C  
the EEPROM to the SRAM (the  
F CECC 90000 Quality Standard  
F ESD characterization according  
MIL STD 883C M3015.7-HB  
(classification see IC Code  
Numbers)  
RECALL operation) take place  
automatically on power up. The  
U632H64 combines the high per-  
formance and ease of use of a fast  
SRAM with nonvolatile data inte-  
F Packages:PDIP28 (300 mil)  
PDIP28 (600 mil)  
grity.  
STORE cycles also may be initia-  
SOP28 (330 mil)  
ted under user control via a soft-  
Pin Configuration  
Pin Description  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
VCAP  
A12  
A7  
VCCX  
W
2
Signal Name Signal Description  
3
HSB  
A8  
A0 - A12  
Address Inputs  
Data In/Out  
4
A6  
DQ0 - DQ7  
5
A5  
A9  
6
A4  
Chip Enable  
A11  
G
E
PDIP  
SOP  
7
A3  
Output Enable  
Write Enable  
G
8
A2  
A10  
E
W
9
A1  
VCCX  
VSS  
VCAP  
Power Supply Voltage  
Ground  
10  
11  
12  
13  
14  
A0  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
DQ0  
DQ1  
DQ2  
VSS  
Capacitor  
Hardware Controlled Store/Busy  
HSB  
Top View  
November 01, 2001  
1

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