U632H64
PowerStore 8K x 8 nvSRAM
Not Recommended For New Designs
Features
Description
High-performance CMOS non-
volatile static RAM 8192 x 8 bits
25 ns Access Time
12 ns Output Enable Access
Time
ICC = 15 mA at 200 ns Cycle
Time
Automatic STORE to EEPROM
on Power Down using external
capacitor
The U632H64 has two separate ware sequence or via a single pin
modes of operation: SRAM mode (HSB).
and nonvolatile mode. In SRAM Once a STORE cycle is initiated,
mode, the memory operates as an further input or output are disabled
ordinary static RAM. In nonvolatile until the cycle is completed.
operation, data is transferred in Because a sequence of addresses
parallel from SRAM to EEPROM or is used for STORE initiation, it is
from EEPROM to SRAM. In this important that no other read or
mode SRAM functions are disab- write accesses intervene in the
led.
sequence or the sequence will be
Hardware or Software initiated
STORE
The U632H64 is a fast static RAM aborted.
(25 ns), with a nonvolatile electri- RECALL cycles may also be initia-
cally erasable PROM (EEPROM) ted by a software sequence.
element incorporated in each static Internally, RECALL is a two step
memory cell. The SRAM can be procedure. First, the SRAM data is
read and written an unlimited num- cleared and second, the nonvola-
ber of times, while independent tile information is transferred into
(STORE Cycle Time < 10 ms)
Automatic STORE Timing
105 STORE cycles to EEPROM
10 years data retention in
EEPROM
Automatic RECALL on Power Up nonvolatile
data
resides
in the SRAM cells.
Software RECALL Initiation
(RECALL Cycle Time < 20 μs)
Unlimited RECALL cycles from
EEPROM
EEPROM. Data transfers from the The RECALL operation in no way
SRAM to the EEPROM (the alters the data in the EEPROM
STORE operation) take place auto- cells. The nonvolatile data can be
matically upon power down using recalled an unlimited number of
charge stored in an external 100 times.
μF capacitor. Transfers from the
EEPROM to the SRAM (the
RECALL operation) take place
automatically on power up. The
U632H64 combines the high per-
Single 5 V 10 % Operation
Operating temperature ranges:
0 to 70 °C
-40 to 85 °C
QS 9000 Quality Standard
ESD characterization according
MIL STD 883C M3015.7-HB
(classification see IC Code
Numbers)
formance and ease of use of a fast
SRAM with nonvolatile data inte-
grity.
RoHS compliance and Pb- free
Package: SOP28 (330 mil)
STORE cycles also may be initia-
ted under user control via a soft-
Pin Configuration
Pin Description
1
VCAP
A12
A7
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCCX
W
2
3
Signal Name Signal Description
HSB
A8
4
A6
A0 - A12
Address Inputs
Data In/Out
5
A5
A9
DQ0 - DQ7
6
A4
A11
G
Chip Enable
E
7
A3
Output Enable
Write Enable
G
8
SOP
A2
A10
E
W
9
A1
10
11
12
13
14
A0
VCCX
VSS
VCAP
Power Supply Voltage
Ground
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
VSS
Capacitor
Hardware Controlled Store/Busy
HSB
Top View
August 15, 2006
STK Control #ML0047
1
Rev 1.1