U3661M

更新时间： 2024-01-10 14:06:39

品牌	Logo	应用领域
TEMIC		延迟线
页数	文件大小	规格书
9页	139K
描述
Baseband Delay Line

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技术参数
数据手册

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U3661M 技术参数

生命周期：	Transferred	包装说明：	SO-16
Reach Compliance Code：	unknown	风险等级：	5.69
其他特性：	OUTPUT TYPE CAN ALSO BE (-R-Y; -B-Y)	商用集成电路类型：	COLOR SIGNAL DECODER
JESD-30 代码：	R-PDSO-G16	功能数量：	1
端子数量：	16	最高工作温度：	70 °C
最低工作温度：	-10 °C	封装主体材料：	PLASTIC/EPOXY
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
认证状态：	Not Qualified	最大压摆率：	10 mA
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子位置：	DUAL
Base Number Matches：	1

U3661M 数据手册

U3661M

Baseband Delay Line (64 s)

Application

In TV sets, the integrated baseband delay line circuit is suitable for decoders with color-difference signal outputs

Description

The integrated delay line circuit U3661M is suitable for A summing circuitry combines the information of

all chroma decoders with baseband color-difference adjacent TV-lines, thus giving an interpolated sum for the

outputs. It is suitable for PAL-, SECAM- and PAL-system, storing preceeding lines for the SECAM-

NTSC-signals as well. The U3661M contains two system and providing a comb-filtered output for

separate delay lines for processing (R–Y)-output and NTSC-signals. Due to internally-generated timing,

(B–Y)-output separately. The delay is performed by synchronization is easily done by feeding a line-frequent

internally switched capacitors. On-chip postfiltering impulse (usually the SC-impulse) to the sync-input of

avoids the need for external filter components.

the IC.

Features

One line delay time, addition of delayed and

non-delayed output signals

Line-locked by the sandcastle pulse

No crosstalk between SECAM color

carriers (diaphoty)

Adjustment-free application, VCO without

external components

Comb filtering functions for NTSC

color-difference signals

Handles negative or positive color-difference

input signals

Clamping of ac-coupled input signals

Correction of phase errors in the PAL system

[±(R–Y) and ±(B–Y)]

Ref

(B–Y)

S+H

LPF

Clamping

Line memory

Shift register

Line memory

(R–Y)

S+H

LPF

Clamping

Bias

Ref

3 MHz

Control

DD2

DD1

PLL

SC detector

Clock generator

GND1

GND2

94 8846

SC pulse

Figure 1. Block diagram

TELEFUNKEN Semiconductors

1 (9)

Rev. A1, 17-Jul-96

Preliminary Information

12 3 4 5 6 7...9

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