TUSB212
www.ti.com.cn
ZHCSGM7A –AUGUST 2017–REVISED SEPTEMBER 2017
5 Pin Configuration and Functions
RWB Package
12 Pin (X2QFN)
Top View
D1P D1M
VCC
3
4
5
6
12
SDA
SCL/CD
RSTN
EQ
2
1
11 VREG
10 GND
DC_BOOST/
ENA_HS
7
8
9
D2P D2M
Pin Functions
PIN
INTERNAL
PULLUP/PULLDOWN
I/O
DESCRIPTION
NAME
D1M
NO.
1
I/O
I/O
N/A
N/A
USB High Speed negative port..
USB High Speed positive port.
I2C Mode:
D1P
2
Bidirectional I2C data pin [I2C address = 0x2C].
In non I2C mode:
Reserved for TI test purpose.
SDA(1)
3
4
I/O
RSTN asserted: 500 kΩ PD
In I2C mode:
I2C clock pin [I2C address = 0x2C].
Non I2C mode:
After reset: Output CD. Flag indicating that a USB device is attached (connection
detected). Asserted from an unconnected state upon detection of DP or DM pull-up
resistor. De-asserted upon detection of disconnect.
SCL(1)/CD
I/O
RSTN asserted: 500 kΩ PD
Device disable/enable.
Low – Device is at reset and in shutdown, and
High – Normal operation.
RSTN
EQ
5
6
I
I
500 kΩ PU
Recommend 0.1-µF external capacitor to GND to ensure clean power on reset if not
driven.
If the pin is driven, it must be held low until the supply voltage for the device reaches
within specifications.
USB High Speed AC boost select via external pull down resistor.
Sampled upon de-assertion of RSTN. Does not recognize real time adjustments.
Auto selects max AC Boost when left floating.
N/A
D2P
D2M
7
8
I/O
I/O
N/A
N/A
USB High Speed positive port.
USB High Speed negative port.
In I2C mode:
Reserved for TI test purpose.
In non-I2C mode:
At reset: 3-level input signal DC_BOOST. USB High Speed DC signal boost selection.
H (pin is pulled high) – 80 mV
M (pin is left floating) – 60 mV
L (pin is pulled low) – 40 mV
After reset: Output signal ENA_HS. Flag indicating that channel is in High Speed mode.
Asserted upon:
DC_BOOST(2)
ENA_HS
/
9
I/O
1. Detection of USB-IF High Speed test fixture from an unconnected state followed by
transmission of USB TEST_PACKET pattern.
2. Squelch detection following USB reset with a successful HS handshake [HS
handshake is declared to be successful after single chirp J chirp K pair where each chirp
is within 18 μs – 128 μs].
GND
VREG
VCC
10
11
12
P
O
P
N/A
N/A
N/A
Ground
1.8-V LDO output. Only enabled when operating in High Speed mode. Requires 0.1-µF
external capacitor to GND to stabilize the core.
Supply power
(1) Pull-up resistors for SDA and SCL pins in I2C mode should be 4.7 kΩ (5%). If both SDA and SCL are pulled up at reset the device
enters into I2C mode.
(2) Pull-down and pull-up (to 3.3 V) resistors for DC_BOOST pins must be between 22 kΩ to 47 kΩ in non I2C mode.
Copyright © 2017, Texas Instruments Incorporated
3