TUSB1004
ZHCSMM7 –APRIL 2022
www.ti.com.cn
表4-1. Pin Functions (continued)
PIN
NAME
TYPE(1)
DESCRIPTION
NO.
SSTX2p
9
Differential positive input for USB port 2. Should be connected to USB 3.2 Host transmit
port through an external 220 nF AC-coupling capacitor.
I
I
SSTX2n
10
Differential positive input for USB port 2. Should be connected to USB 3.2 Host transmit
port through an external 220 nF AC-coupling capacitor.
NC
11
12
No internal connection.
SSRX2p
Differential positive output for USB port 2. Should be connected to USB 3.2 Host receiver
port through an external 220 nF AC-coupling capacitor.
O
O
SSRX2n
VIO_SEL
13
14
Differential negative output for USB port 2. Should be connected to USB 3.2 Host receiver
port through an external 220 nF AC-coupling capacitor.
Selects the input thresholds for I2C (SDA and SCL).
"0": I2C 3.3 V
"R": I2C 1.8 V
"F": I2C 3.3 V.
"1": I2C 1.8 V.
4-level I
(PU/PD)
SSTX1p
SSTX1n
MODE
15
16
17
18
19
Differential positive input for USB port 1. Should be connected to USB 3.2 Host transmit
port through an external 220 nF AC-coupling capacitor.
I
I
Differential negative input for USB port 1. Should be connected to USB 3.2 Host transmit
port through an external 220 nF AC-coupling capacitor.
This pin selects whether device is in I2C mode or pin-strap mode. Refer to 表7-4 for
details.
4-level I
(PU/PD)
SSRX1p
SSRX1n
Differential positive output for USB port 1. Should be connected to USB 3.2 Host receiver
port through an external 220 nF AC-coupling capacitor.
O
Differential negative output for USB port 1. Should be connected to USB 3.2 Host receiver
port through an external 220 nF AC-coupling capacitor.
O
P
VCC
20
21
3.3 V supply
TEST2/SCL
In I2C mode, this pin functions as I2C clock.
I
In pin-strap mode, this pin is used for TI internal test and should be pull-down or tied to
GND for normal operation.
AEQENZ/SDA
AEQCFG
22
23
In I2C mode, this pin functions as I2C data. In pin-strap mode, this pin controls whether or
not AEQ is enabled.
0: AEQ enabled
1: AEQ disabled
I/O
In pin-strap mode, this pin controls the FULLAEQ_UPPER_EQ limit. In I2C mode, this
function is controlled by the FULLAEQ_UPPER_EQ register.
"0": FULLAEQ_UPPER_EQ = Ah
4-level I
(PU/PD)
"R": FULLAEQ_UPPER_EQ = Fh
"F": FULLAEQ_UPPER_EQ = 8h
"1": FULLAEQ_UPPER_EQ = Ch
NC
NC
EN
24
25
26
No internal connection
No internal connection
When low, the differential receiver's termination will be disabled and differential drivers will
be disabled. On rising edge of EN, device will sample four-level inputs and function based
on the sampled state of the pins. This pin has a internal 500k pull-up to VCC. Please note
this pin will also reset internal configuration registers.
I
(PU)
TEST1
VCC
27
28
29
I
TI Test1. Under normal operations this pin shall be connected directly or pulled up to VCC.
3.3 V supply
P
CEQ1
In pin-strap mode, this pin along with CEQ0 selects the receiver EQ for CRX1 and/or
CRX2 (Refer to 表7-2).
4-level I
(PU/PD)
CRX1n
30
Differential negative input for USB port 1. Should be connected to SSRXn pin of USB
connector. Connection can be DC-coupled to USB connector. Optionally, connection can
be through an external 330 nF AC-coupling capacitor.
I
Copyright © 2022 Texas Instruments Incorporated
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