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TUSB1002IRMQT PDF预览

TUSB1002IRMQT

更新时间: 2024-02-04 13:41:03
品牌 Logo 应用领域
德州仪器 - TI 接口集成电路
页数 文件大小 规格书
34页 2171K
描述
USB3.1 10Gbps Dual Channel Linear Redriver 24-WQFN -40 to 85

TUSB1002IRMQT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete包装说明:,
Reach Compliance Code:compliant风险等级:5.72
接口集成电路类型:LINE TRANSCEIVERJESD-609代码:e4
湿度敏感等级:2端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
Base Number Matches:1

TUSB1002IRMQT 数据手册

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TUSB1002  
www.ti.com  
SLLSEU4D MAY 2016REVISED OCTOBER 2017  
Pin Functions (continued)  
PIN  
INTERNAL PULLUP  
TYPE  
DESCRIPTION  
PULLDOWN  
NAME  
RGE  
EN. Places TUSB1002 into shutdown mode when asserted low. Normal  
operation when pin is asserted high. When in shutdown, TUSB1002’s receiver  
terminations will be high impedance and tx/rx channels will be disabled.  
EN  
5
I (2-level)  
PU (approx 400 K)  
CFG1. This pin along with CFG2 will select VOD linearity range and DC gain  
for both channels 1 and 2. The state of this pin is sampled after the rising edge  
of EN. Refer to Figure 2 for details of timing. Refer to Table 3 for VOD linearity  
range and DC gain options.  
CFG1  
CFG2  
4
I (4-level)  
I (4-level)  
PU (approx 45K)  
PD (approx 95K)  
CFG2. This pin along with CFG1 will set VOD linearity range and DC gain for  
both channels 1 and 2. The state of this pin is sampled after the rising edge of  
EN. Refer to Figure 2 for details of timing. Refer to Table 3 for VOD linearity  
range and DC gain options.  
15  
MODE. This pin is for selecting different modes of operation. The state of this  
pin is sampled after the rising edge of EN. Refer to Figure 2 for details of  
timing.  
PU (approx 45 K)  
PD (approx 95K)  
MODE  
7
I (4-level)  
0 = Test Mode. TI Internal Use Only.  
R = PCIe / Test Mode. PCIe Mode and TI Internal use only  
F = USB3.1 Dual Channel Operation enabled (TUSB1002 normal mode).  
1 = USB3.1 Single-channel operation.  
RSVD1. Under normal operation, this pin will be driven low by TUSB1002.  
Recommend leaving this pin unconnected on PCB.  
RSVD1  
24  
O
SLP_S0#. This pin when asserted low will disable Receiver Detect functionality.  
While this pin low and TUSB1002 is in U2/U3, TUSB1002 disables LOS and  
LFPS detection circuitry and Rx termination for both channels will remain  
enabled. If this pin is low and TUSB1002 is in Disconnect state, the Rx detect  
functionality is disabled and Rx termination for both channels will be disabled. If  
the system SoC does not support a GPIO that indicates system sleep state,  
then it is recommended to leave this pin unconnected.  
SLP_S0#  
14  
I (2-level)  
PU (approx 400 K)  
0 – Rx Detect disabled  
1 – Rx Detect enabled  
NC  
No Connect. Leave unconnected on PCB.  
3.3 V (±10%) Supply.  
VCC  
1, 13  
Power  
GND  
6, 10, 18,  
21  
GND  
Ground  
Thermal pad  
Thermal pad. Recommend connecting to a solid ground plane.  
Copyright © 2016–2017, Texas Instruments Incorporated  
Submit Documentation Feedback  
5
Product Folder Links: TUSB1002  

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