TQM879026
0.7−4 GHz ¼W Digital Variable Gain Amplifier
Serial Control Interface
The TQM879026 has a CMOS SPITM input compatible serial interface. This serial control interface converts the
serial data input stream to parallel output word. The input is 3-wire (CLK, LE and SID) SPITM input compatible. At
power up, the serial control interface resets the DSA to the minimum gain state. The 6-bit SID (Serial Input Data)
word is loaded into the register on rising edge of the CLK, MSB first. When LE is high, CLK is internally disabled.
Serial Control Timing Characteristics (Test conditions: VDD = +5 V, Temp.=25°C)
Units
MHz
ns
Parameter
Condition
Min
Max
Clock Frequency
50% Duty Cycle
10
LE Setup Time, tLESUP
LE Pulse Width, tLEPW
SID set-up time, tSDSUP
SID hold-time, tSDHLD
LE Pulse Spacing tLE
Propagation Delay tPLO
after last CLK rising edge
10
30
ns
before CLK rising edge
after CLK rising edge
LE to LE pulse spacing
LE to Parallel output valid
10
ns
10
ns
630
ns
30
ns
Serial Control DC Logic Characteristics (Test conditions: VDD = +5 V, Temp.=25°C)
Parameter
Condition
Min
0
Max
0.8
Units
Input Low State Voltage, VIL
Input High State Voltage, VIH
Output High State Voltage, VOH
Output Low State Voltage, VOL
Input Current, IIH / IIL
V
2.4
2.0
0
VDD
VDD
0.8
V
On SOD pin
V
On SOD pin
V
On SID, LE and CLK pins
−10
+10
µA
SID Control Logic Truth Table
Timing Diagram
CLK is internally disabled when LE is high
6-Bit Control Word
Gain Relative to
Maximum Gain
MSB
D5
1
LSB
D0
1
D5-D0
MSB-LSB
D5-D0
MSB-LSB
D4
1
D3
1
D2
1
D1
1
Maximum Gain
−0.5 dB
−1 dB
1
1
1
1
1
0
1
1
1
1
0
1
LE
tPLO
1
1
1
0
1
1
−2 dB
CLK
1
1
0
1
1
1
−4 dB
1
0
1
1
1
1
−8 dB
0
1
1
1
1
1
−16 dB
−31.5 dB
SID
0
0
0
0
0
0
tLESUP
tSDSUP
tSDHLD
tLEPW
Any combination of the possible 64 states will provide a
reduction in gain of approximately the sum of the bits
selected.
Data Sheet: Rev B 12/14/2012
- 3 of 8 -
Disclaimer: Subject to change without notice
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© 2012 TriQuint Semiconductor, Inc.