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TPS71701DCKTG4 PDF预览

TPS71701DCKTG4

更新时间： 2024-01-03 21:53:26
品牌 Logo 应用领域
德州仪器 - TI 线性稳压器IC调节器电源电路光电二极管输出元件信息通信管理
页数 文件大小 规格书
27页 960K
描述
Low Noise, High-Bandwidth PSRR Low-Dropout 150mA Linear Regulator

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TPS71701DCKTG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SC-70, 5 PIN针数：5
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：5.12Is Samacsys：N
可调性：ADJUSTABLE最大回动电压 1：0.3 V
标称回动电压 1：0.17 V最大输入电压：6.5 V
最小输入电压：2.5 VJESD-30 代码：R-PDSO-G5
JESD-609代码：e4长度：2 mm
湿度敏感等级：1功能数量：1
输出次数：1端子数量：5
工作温度TJ-Max：125 °C工作温度TJ-Min：-40 °C
最高工作温度：125 °C最低工作温度：-40 °C
最大输出电流 1：0.15 A最大输出电压 1：6.2 V
最小输出电压 1：0.9 V封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP5/6,.08
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TR峰值回流温度（摄氏度）：260
认证状态：Not Qualified调节器类型：ADJUSTABLE POSITIVE SINGLE OUTPUT LDO REGULATOR
座面最大高度：1.1 mm子类别：Other Regulators
表面贴装：YES技术：BICMOS
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：1.25 mm
Base Number Matches：1

TPS71701DCKTG4 数据手册

 浏览型号TPS71701DCKTG4的Datasheet PDF文件第1页浏览型号TPS71701DCKTG4的Datasheet PDF文件第3页浏览型号TPS71701DCKTG4的Datasheet PDF文件第4页浏览型号TPS71701DCKTG4的Datasheet PDF文件第5页浏览型号TPS71701DCKTG4的Datasheet PDF文件第6页浏览型号TPS71701DCKTG4的Datasheet PDF文件第7页 
TPS717xx  
www.ti.com  
SBVS068D–FEBRUARY 2006–REVISED OCTOBER 2007  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with  
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more  
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.  
ORDERING INFORMATION(1)  
(2)  
PRODUCT  
VOUT  
TPS717xxyyyz  
XX is nominal output voltage (for example, 28 = 2.8V, 285 = 2.85V, 01 = Adjustable).  
YYY is package designator.  
Z is package quantity.  
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI  
website at www.ti.com.  
(2) Output voltages from 0.9V to 3.3V in 50mV increments are available through the use of innovative factory EEPROM programming;  
minimum order quantities may apply. Contact factory for details and availability.  
ABSOLUTE MAXIMUM RATINGS(1)  
Over operating temperature range (unless otherwise noted). All voltages are with respect to GND.  
PARAMETER  
TPS717xx  
–0.3 to +7.0  
UNIT  
Input voltage range, VIN  
V
V
V
V
Feedback input voltage range, VFB, VNR  
Enable voltage range, VEN  
Output voltage range, VOUT  
Maximum output current, IOUT  
Continuous total power dissipation, PDISS  
Junction temperature range, TJ  
Storage junction temperature range, TSTG  
ESD rating, HBM  
–0.3 to +3.6  
–0.3 to VIN + 0.3V(2)  
–0.3 to +7.0  
Internally limited  
See Dissipation Ratings Table  
–55 to +150  
°C  
°C  
kV  
V
–55 to +150  
2
ESD rating, CDM  
500  
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may  
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond  
those specified is not implied.  
(2) VEN absolute maximum rating is VIN + 0.3V or +7.0V, whichever is greater.  
DISSIPATION RATINGS  
DERATING FACTOR  
BOARD  
Low-K(1)  
High-K(2)  
Low-K(1)  
High-K(2)  
High-K(2)  
PACKAGE  
DCK  
RθJC  
165°C/W  
165°C/W  
20°C/W  
20°C/W  
—
RθJA  
ABOVE TA = +25°C  
TA < +25°C  
250mW  
TA = +70°C  
140mW  
175mW  
395mW  
845mW  
269mW  
TA = +85°C  
100mW  
130mW  
285mW  
615mW  
194mW  
395°C/W  
315°C/W  
140°C/W  
65°C/W  
206°C/W  
2.5mW/°C  
DCK  
3.2mW/°C  
320mW  
DRV  
7.1mW/°C  
715mW  
DRV  
15.4mW/°C  
4.85mW/°C  
1540mW  
485mW  
DSE  
(1) The JEDEC low-K (1s) board used to derive this data was a 3in × 3in, two-layer board with 2-ounce copper traces on top of the board.  
(2) The JEDEC high-K (2s2p) board used to derive this data was a 3in × 3in, multilayer board with 1-ounce internal power and ground  
planes and 2-ounce copper traces on top and bottom of the board.  
2
Submit Documentation Feedback  
Copyright © 2006–2007, Texas Instruments Incorporated  
 
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TPS71701DCKTG4 替代型号

型号 品牌 替代类型 描述 数据表
TPS71701DCKT TI

类似代替

 		Low Noise, High-Bandwidth PSRR Low-Dropout 150mA Linear Regulator
TPS71701DCKR TI

类似代替

 		Low Noise, High-Bandwidth PSRR Low-Dropout 150mA Linear Regulator

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