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TPS65721RSNR PDF预览

TPS65721RSNR

更新时间： 2024-02-20 18:07:25
品牌 Logo 应用领域
德州仪器 - TI 电信集成电路电信电路PC蓝牙
页数 文件大小 规格书
50页 1633K
描述
PMU for Bluetooth Headsets

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TPS65721RSNR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN,针数：32
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：1.25JESD-30 代码：S-PQCC-N32
JESD-609代码：e4长度：4 mm
湿度敏感等级：2功能数量：1
端子数量：32最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：0.8 mm
标称供电电压：3.6 V表面贴装：YES
电信集成电路类型：TELECOM CIRCUIT温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：NO LEAD
端子节距：0.4 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4 mm
Base Number Matches：1

TPS65721RSNR 数据手册

 浏览型号TPS65721RSNR的Datasheet PDF文件第1页浏览型号TPS65721RSNR的Datasheet PDF文件第2页浏览型号TPS65721RSNR的Datasheet PDF文件第3页浏览型号TPS65721RSNR的Datasheet PDF文件第5页浏览型号TPS65721RSNR的Datasheet PDF文件第6页浏览型号TPS65721RSNR的Datasheet PDF文件第7页 
TPS65720  
TPS65721  
SLVS979 –OCTOBER 2009  
www.ti.com  
ELECTRICAL CHARACTERISTICS (continued)  
VSYS = 3.6V, VDCDC1 = 2.05V, PFM mode, L = 3.3μH, COUTDCDC1 = 4.7μF, VINLDO1=2.05V, VLDO1=1.85V, TA = –40°C to 85°C  
typical values apply in a temperature range of 10°C to 35°C (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
SDAT, SCLK, PB_IN, HOLD, GPIO0 TO GPIO3, INT, RESET, THRESHOLD  
High level input voltage for SCLK, SDAT, GPIOx,  
VIH  
GPIOs configured as input  
1.2  
0
VSYS  
0.4  
V
V
V
HOLD_DCDC1, HOLD_LDO1, PB_IN  
Low level input voltage for SCLK, SDAT, GPIOx,  
HOLD_DCDC1, HOLD_LDO1, PB_IN  
VIL  
GPIOs configured as input  
Low level output voltage for SDAT, GPIOx, INT,  
RESET  
VOL  
GPIOs configured as output; Io=1mA; no internal pull-up  
0
0.4  
GPIO2, GPIO3 configured as current sink; VOL=0.4V ; for  
Tj=0°C to 85°C  
Sink current for GPIO2, GPIO3  
Sink current for GPIOx  
–20%  
5
20%  
3
mA  
mA  
IOL  
GPIOx configured as open drain output ; output = LOW  
Minimum voltage for proper current regulation from  
GPIO2 or GPIO3 to GND if programmed as a  
current sink  
VOL  
Io=5mA; current sink turned on  
0.4  
V
VLDO1,  
nom-13%  
VLDO1,  
nom-7%  
VRESET-falling  
VRESET-rising  
Falling edge; Reset is asserted LOW for TPS65720  
V
V
LDO1 out of regulation reset voltage  
Reset delay time on pin RESET  
Rising edge; Reset is released HIGH for TPS65720 after  
TRESET  
VLDO1,  
nom-4%  
Low to high transition of RESET pin, depending on setting of  
Bit RESET_DELAY  
9
70  
11  
90  
13  
110  
ms  
TRESET  
HIGH to LOW transition of RESET pin RESET will go low by  
HOLD pin going LOW AND HOLD Bit set to 0 OR voltage at  
Vreset falling below the threshold  
10  
μs  
VTHRESHOLD_down Threshold voltage for reset input  
VTHRESHOLD_hys Hysteresis on THRESHOLD  
Falling voltage; QFN package only  
Rising voltage; QFN package only  
Rising and falling voltage  
–3%  
39  
570  
30  
3%  
mV  
mV  
ms  
Tdebounce  
ILKG  
Debounce time at PB_IN  
Input leakage current  
50  
60  
PB_IN, SDAT, SCLK, GPIOx configured as output, INT,  
RESET, output high impedance  
0.2  
μA  
STEP-DOWN CONVERTER  
VSYS  
Input voltage for DCDC1  
2.3  
5.6  
V
V
VSYS falling  
VSYS rising  
2.15  
2.2  
2.25  
UVLO  
Internal undervoltage lockout threshold hysteresis  
120  
mV  
POWER SWITCH  
RDS(ON)  
ILK_HS  
VSYS = VINDCDC1 = 3.6V, YFF package  
VSYS = VINDCDC1 = 3.6V, RSN package  
VDS = 5.6V  
350  
400  
600  
650  
1
High side MOSFET on-resistance  
High side MOSFET leakage current  
Low side MOSFET on-resistance  
Low side MOSFET leakage current  
mΩ  
μA  
mΩ  
mΩ  
μA  
VINDCDC1/2 = 3.6 V, YFF package  
VINDCDC1/2 = 3.6 V, RSN package  
VDS = 5.6 V  
300  
350  
500  
550  
1
RDS(ON)  
ILK_LS  
2.3 V ≤ VIN ≤ 5.6 V, TPS65720  
2.3 V ≤ VIN ≤ 5.6 V, TPS65721  
VSYS > 2.7 V; TPS65720  
425  
625  
600  
850  
775  
1150  
200  
400  
mA  
mA  
Forward current limit high-side and low side  
MOSFET  
ILIMF  
Io  
DC output current  
mA  
VSYS > 2.7 V ; TPS65721  
OSCILLATOR  
fSW  
Oscillator Frequency  
2.03  
0.6  
2.25  
2.48  
Vin  
MHz  
OUTPUT  
VOUT  
VFB  
Output Voltage Range  
Feedback voltage  
V
V
0.6  
1%  
0.5  
IFB  
FB pin input current  
0.1  
3%  
2%  
μA  
VIN = 2.3 V to 5.6 V; PFM operation, 0 mA < IOUT < IOUTMAX  
VIN = 2.3 V to 5.6 V, PWM operation, 0 mA < IOUT < IOUTMAX  
PWM operation  
DC Output voltage accuracy(1)  
VOUT  
–2%  
DC output voltage load regulation  
%/A  
V
VDCDC1,  
nom-14%  
VDCDC1,  
nom-7%  
VPGOOD-falling  
VPGOOD-rising  
PGOOD threshold at falling output voltage  
<PGOODZ_DCDC1> is set to 1  
<PGOODZ_DCDC1> is set to 0  
VDCDC1,  
nom-5%  
PGOOD threshold at rising output voltage  
V
tStart  
Start-up time  
Time from active EN to Start switching  
Time to ramp from 5% to 95% of VOUT  
170  
250  
μs  
μs  
tRamp  
VOUT ramp time  
(1) Output voltage specification does not include tolerance of external voltage programming resistors  
Submit Documentation Feedback  
4
Copyright © 2009, Texas Instruments Incorporated  
Product Folder Link(s): TPS65720 TPS65721  
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