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TPS62004DGSRG4

更新时间： 2024-02-19 05:01:50
品牌 Logo 应用领域
德州仪器 - TI 转换器稳压器开关式稳压器或控制器电源电路开关式控制器光电二极管功效DC-DC转换器
页数 文件大小 规格书
25页 469K
描述
HIGH-EFFICIENCY STEP-DOWN LOW POWER DC-DC CONVERTER

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TPS62004DGSRG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：MSOP
包装说明：TSSOP, TSSOP10,.19,20针数：10
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：5.18其他特性：PFM CONTROL TECHNIQUE IS ALSO POSSIBLE
模拟集成电路 - 其他类型：SWITCHING REGULATOR控制模式：CURRENT-MODE
控制技术：PULSE WIDTH MODULATION最大输入电压：5.5 V
最小输入电压：2 V标称输入电压：3.6 V
JESD-30 代码：S-PDSO-G10JESD-609代码：e4
长度：3 mm湿度敏感等级：1
功能数量：1端子数量：10
最高工作温度：85 °C最低工作温度：-40 °C
最大输出电流：1.6 A最大输出电压：1.56 V
最小输出电压：1.455 V标称输出电压：1.5 V
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP10,.19,20封装形状：SQUARE
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.1 mm
子类别：Switching Regulator or Controllers表面贴装：YES
切换器配置：BUCK最大切换频率：1000 kHz
技术：MOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3 mm
Base Number Matches：1

TPS62004DGSRG4 数据手册

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SLVS294C − SEPTEMBER 2000 − REVISED SEPTEMBER 2003  
Terminal Functions  
TERMINAL  
NO.  
DGS  
I/O  
DESCRIPTION  
NAME  
YEG  
EN  
8
5
2
B3  
I
I
Enable. A logic high enables the converter, logic low forces the device into shutdown mode reducing the  
supply current to less than 1 µA.  
FB  
FC  
A2  
C1  
Feedback pin for the fixed output voltage option. For the adjustable version an external resistive divider is  
connected to FB. The internal voltage divider is disabled for the adjustable version.  
Supply bypass pin. A 0.1 µF coupling capacitor should be connected as close as possible to this pin for good  
high frequency input voltage supply filtering.  
GND  
ILIM  
3
6
A1  
A3  
Ground  
I
Switch current limit. Connect ILIM to GND to set the switch current limit to typically 600 mA, or connect this  
pin to V to set the current limit to typically 1200 mA.  
IN  
L
9
4
C2,  
C3  
I/O  
O
Connect the inductor to this pin. L is the switch pin connected to the drain of the internal power MOSFETS.  
PG  
B1  
Power good comparator output. This is an open-drain output. A pullup resistor should be connected  
between PG and V . The output goes active high when the output voltage is greater than 92% of the nominal  
O
value.  
PGND  
SYNC  
10  
7
D2  
D3  
Power ground. Connect all power grounds to PGND.  
I
I
Input for synchronization to external clock signal. Synchronizes the converter switching frequency to an  
external clock signal with CMOS level:  
SYNC = HIGH: Low-noise mode enabled, fixed frequency PWM operation is forced  
SYNC = LOW (GND): Power save mode enabled, PFM/PWM mode enabled.  
V
IN  
NC  
1
D1  
B2  
Supply voltage input  
Not connected  
detailed description  
operation  
The TPS6200x is a step down converter operating in a current mode PFM/PWM scheme with a typical switching  
frequency of 750 kHz.  
At moderate to heavy loads, the converter operates in the pulse width modulation (PWM) and at light loads the  
converter enters a power save mode (pulse frequency modulation) to keep the efficiency high.  
In the PWM mode operation, the part operates at a fixed frequency of 750 kHz. At the beginning of each clock  
cycle, the high side P-channel MOSFET is turned on. The current in the inductor ramps up and is sensed via  
an internal circuit. The high side switch is turned off when the sensed current causes the PFM/PWM comparator  
to trip when the output voltage is in regulation or when the inductor current reaches the current limit (set by ILIM).  
After a minimum dead time preventing shoot through current, the low side N-channel MOSFET is turned on and  
the current ramps down again. As the clock cycle is completed, the low side switch is turned off and the next  
clock cycle starts.  
In discontinuous conduction mode (DCM), the inductor current ramps to zero before the end of each clock cycle.  
In order to increase the efficiency the load comparator turns off the low side MOSFET before the inductor current  
becomes negative. This prevents reverse current flowing from the output capacitor through the inductor and  
low side MOSFET to ground that would cause additional losses.  
As the load current decreases and the peak inductor current does not reach the power save mode threshold  
of typically 120 mA for more than 15 clock cycles, the converter enters a pulse frequency modulation (PFM)  
mode.  
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...25

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