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TPS62000SHKK

更新时间： 2024-02-14 23:24:10

品牌	Logo	应用领域
德州仪器 - TI		转换器功效 DC-DC转换器
页数	文件大小	规格书
22页	534K
描述
HIGH-EFFICIENCY STEP-DOWN LOW POWER DC-DC CONVERTER

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数据手册

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TPS62000SHKK 数据手册

TPS62000-HT

www.ti.com .......................................................................................................................................................... SLVS917A–MARCH 2009–REVISED JUNE 2009

FUNCTIONAL BLOCK DIAGRAM

FC (See Note B)

Undervoltage

Lockout

10 Ω

Bias Supply

Current

Sense

P-Channel

Slope Compensation

PFM/PWM

Power Good

Power MOSFET

Mode Select

PFM/PWM

Comparator

Error Amplifier

PFM/PWM

Control Logic

Current Limit

Logic

Driver

(See

Shoot-Through

Logic

Note A)

Soft

Compensation

Start

R1 + R2 ≈ 1 MΩ

N-Channel

Power MOSFET

Current Sense

Sync

Load Comparator

ref

= 0.45 V

Offset

Oscillator

PGND

Antiringing

GND

SYNC

A. The adjustable output voltage version does not use the internal feedback resistor divider. The FB pin is directly

connected to the error amplifier.

B. Do not connect the FC pin to an external power source

PIN FUNCTIONS

I/O

DESCRIPTION

NAME

Enable. A logic high enables the converter, logic low forces the device into shutdown mode reducing the supply current

to less than 1 µA.

An external resistive divider is connected to FB. The internal voltage divider is disabled.

Supply bypass pin. A 0.1 µF coupling capacitor should be connected as close as possible to this pin for good high

frequency input voltage supply filtering.

GND

Ground.

I/O

Connect the inductor to this pin. L is the switch pin connected to the drain of the internal power MOSFETS.

Power ground. Connect all power grounds to PGND.

PGND

Input for synchronization to external clock signal. Synchronizes the converter switching frequency to an external clock

signal with CMOS level:

SYNC = HIGH: Low-noise mode enabled, fixed frequency PWM operation is forced.

SYNC

V_IN

SYNC = LOW (GND): Power save mode enabled, PFM/PWM mode enabled.

Supply voltage input.

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