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TPS62000SHKK

更新时间： 2024-02-07 00:11:37

品牌	Logo	应用领域
德州仪器 - TI		转换器功效 DC-DC转换器
页数	文件大小	规格书
22页	534K
描述
HIGH-EFFICIENCY STEP-DOWN LOW POWER DC-DC CONVERTER

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TPS62000SHKK 数据手册

TPS62000-HT

www.ti.com .......................................................................................................................................................... SLVS917A–MARCH 2009–REVISED JUNE 2009

Table 3. Tested Capacitors⁽¹⁾

CAPACITOR VALUE

ESR/mΩ

COMPONENT SUPPLIER

Taiyo Yuden JMK316BJ106KL

Sanyo 6TPA47M

COMMENTS

Ceramic

10 µF

47 µF

68 µF

100

POSCAP

Tantalum

100

Spraque 594D686X0010C2T

(1) Parts are valid for –40°C to 85°C.

INPUT CAPACITOR SELECTION

Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is

required for best input voltage filtering and minimizing the interference with other circuits caused by high input

voltage spikes.

The input capacitor should have a minimum value of 10 µF and can be increased without any limit for better input

voltage filtering.

The input capacitor should be rated for the maximum input ripple current calculated as:

V_O

I_RMS= I_O(max)

´ 1-

(7)

I_O

I_RMS

The worst case RMS ripple current occurs at D = 0.5 and is calculated as:

Ceramic capacitor show a good performance because of their low ESR value, and they are less sensitive against

voltage transients compared to tantalum capacitors.

Place the input capacitor as close as possible to the input pin of the IC for best performance.

LAYOUT CONSIDERATIONS

As for all switching power supplies, the layout is an important step in the design especially at high peak currents

and switching frequencies. If the layout is not carefully done, the regulator might show stability problems as well

as EMI problems.

Therefore, use wide and short traces for the main current paths as indicted in bold in Figure 16. The input

capacitor should be placed as close as possible to the IC pins as well as the inductor and output capacitor. Place

the bypass capacitor, C3, as close as possible to the FC pin. The analog ground, GND, and the power ground,

PGND, need to be separated. Use a common ground node as shown in Figure 16 to minimize the effects of

ground noise.

(ff)

TPS62000

SYNC

GND

PGND

Figure 16. Layout Diagram

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