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TPD2S017_14 PDF预览

TPD2S017_14

更新时间: 2024-11-20 02:58:47
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10页 417K
描述
2-CHANNEL ULTRA-LOW CLAMP VOLTAGE ESD SOLUTION WITH SERIES-RESISTOR ISOLATION

TPD2S017_14 数据手册

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TPD2S017  
www.ti.com .......................................................................................................................................................................................... SLLS949SEPTEMBER 2009  
2-CHANNEL ULTRA-LOW CLAMP VOLTAGE ESD SOLUTION  
WITH SERIES-RESISTOR ISOLATION  
1
FEATURES  
APPLICATIONS  
Hi-Speed USB  
IEEE 1394 Interface  
Low-Voltage Differential Signaling (LVDS)  
Mobile Display Digital Interface (MDDI)/Mobile  
Industry Processor Interface (MIPI)  
Ultra-Low Clamp Voltage Ensures the  
Protection of Ultra-Low Voltage Core Chipset  
During ESD Events  
Exceeds ESD Protection to IEC61000-4-2  
(Level 4)  
HS Signal  
Matching of Series Resistor (R =1 ) of ±8 mΩ  
(Typical)  
DBV PACKAGE  
(TOP VIEW)  
Differential Channel Input Capacitance  
Matching of 0.02 pF (Typical)  
High-Speed Data Rate and EMI Filter Action at  
High Frequencies (–3 dB Bandwidth, 3 GHz)  
Ch1_Out  
GND  
1
2
3
6
5
4
Ch2_Out  
Available in 6-Pin Small-Outline Transistor  
[SOT (DBV)] Package  
V
CC  
Flow-Through Single-In-Line Pin Mapping for  
the High-Speed Lines Ensures no Additional  
Board Layout Burden While Placing the ESD  
Protection Chip Near the Connector  
Ch1_In  
Ch2_In  
DESCRIPTION/ORDERING INFORMATION  
The TPD2S017 provides a robust system-level ESD solution for the high-speed lines interfacing low-voltage,  
ESD-sensitive core chipset. This device offers two stage ESD clamps in each line with 1-series resistor  
isolation. This architecture allows the device to generate very low clamp voltage during system level ESD strikes.  
Due to the series resistor component, the TPD2S017 provides a controlled filter roll-off for even greater spurious  
EMI suppression and signal integrity. This device offers a flow-through pin mapping for ease of board layout. The  
monolithic silicon technology allows matching component values, including clamp capacitance, series resistor  
matching, etc., between the differential signal pairs. Tight matching of the line capacitance and series resistors  
ensure that the differential signal distortion due to added ESD clamp remains minimal, and also allow the part to  
operate at high-speed differential data rate (in excess of 1.5 Gbps).  
The TPD2S017 confirms the IEC61000-4-2 (Level 4) ESD protection and ±15 kV HBM ESD protection. This  
device is offered in space saving DBV packages.  
The TPD2S017 is characterized for operation over ambient air temperature of –40°C to 85°C.  
ORDERING INFORMATION  
TA  
PACKAGE(1)(2)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING  
NFTF  
–40°C to 85°C  
SOT (SOT-23) – DBV  
Reel of 3000  
TPD2S017DBVR  
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.  
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
website at www.ti.com.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2009, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

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